Assume that a cache is direct-mapped and stores 8 blocks. Each block is 16 bytes. Given the following sequence of address requests and assuming the cache starts empty, how many hits are recorded by the cache? Ox10 Ox14 Ox20 0×AO 0x20 Ox10 0×AO 0xAC

Assume that a cache is direct-mapped and stores 8 blocks. Each block is 16 bytes. Given the following sequence of address requests and assuming the cache starts empty, how many hits are recorded by the cache? Ox10 Ox14 Ox20 0×AO 0x20 Ox10 0×AO 0xAC

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache.Tag Index Offset31–10 9–5 4–01. What is the cache block size (in words)?2. How many entries does the cache have?3. What is the ratio between total bits required for such a cache implementation over the data storage bits?Starting from power on, the following byte-addressed cache references are recorded. Address 0 4 16 132 232 160 1024 30 140 3100 180 2180 How many blocks are replaced? What is the hit ratio? List the fi nal state of the cache, with each valid entry represented as a record of <index, tag, data>
What memory blocks will be in the cache after the last address has been accessed?
A cache is set up with a block size of 32 words. There are 16 blocks in cache and set up to be direct map. You have byte address 0x8923. Show the word address, block address, tag, and index. Show each access being filled in with a note of hit or miss. You are given word address and the access are: 0xff, 0x08, 0x22, 0x00, 0x39, 0xF3, 0x07, 0xc0
Please do in correct way!
Assume a direct-mapped cache that holds 4096 bytes, in which each block is 16 bytes.Assuming that an address is 32 bits and that cache is initially empty:a. Complete the table that follows. (You should use hexadecimal numbers for allanswers).b. Which, if any, of the addresses will cause a collision (forcing the block that was justbrought in to be overwritten) if they are accessed one right after the other? Explain
Q e
Suppose you experience a cache miss on a block (let's call it block A). You have accessed block A in the past. There have been precisely 1027 different blocks accessed between your last access to block A and your current miss. Your block size is 64 bytes and you have a 32KB cache. What kind of miss was this? Select one: a. Capacity Miss b. Conflict Miss c. Compulsory Miss
CA_7 Let a program use 5 contiguous words and loop these words 100 times (meaning the execution trace of this program is [012340123401234...1. Furthermore, let a cache have 4 word-sized blocks. How many misses will there be if the cache is: (a)Direct mapped? (b) Fully-associative with commonly used Least-Recently-Used replacement? (c) Fully-associative with less well-known Most-Recently-Used replacement? (d) Set-associative with two sets and uses first-in-first-out replacement? (e) Set-associative with two sets and uses first-in-last-out replacement?
P2
Given a computer with a memory system having a40_bit address, a cache consisting of 8192 blocks each is 32 words. For the following cache types: Direct Mapped (DM), Fully_ associative (FA), Two_way set associative (2_way), Four_way set associative (4_way), Eight_way set associative (8_way), calculate the following values as specified. (Use paper and pencil to do needed calculations and write only the final answer in the given blank space). 1) DM: The size of the index field = Blank 1bits 2) 2_way: The size of the index field =Blank 2bits 3) 4_way: The size of the index field =Blank 3bits 4) 8_way: The size of the index field =Blank 4bits 5) The size of the offset field = Blank 5bits 6) DM: The size of the tag field =Blank 6bits 7) 2_way: The size of the tag field =Blank 7bits 8) 4_way: The size of the tag field =Blank 8bits 9) 8_way: The size of the tag field =Blank 9bits 10) FA: The size of the tag field =Blank 10bits
A cache is set up with a block size of 32 words. There are 64 blocks in cache and set up to be 4-way set associative. You have byte address 0x8923. Show the word address, block address, tag, and index Show each access being filled in with a note of hit or miss. You are given word address and the access are: 0xff, 0x08, 0x22, 0x00, 0x39, 0xF3, 0x07, 0xc0.
Let the cache size be k=3 the initial cache a,b,c and the request a,a,d,e,b,b,a,c,f,d,e,a,f,b,e,c:Request a a d e b b a c f d e a f b e ccache 1 a a d e e e e e e e e e e e e ccache 2 b b b b b b a a a a a a f f f fcache 3 c c c c c c c c f d d d d b b bcache miss x x x x x x x xEight cache misses is a lot better.Selftest: Do the example for LIFO, LFU, RFU and look what happend. code in c++