As described in COD Section 5.7 (Virtual memory), virtual memory uses a page table to track the mapping of virtual addresses tophysical addresses. This exercise shows how this table must be updated as addresses are accessed. The following data constitute astream of virtual byte addresses as seen on a system. Assume 4 KiB pages, a four-entry fully associative TLB, and true LRUreplacement. If pages must be brought in from disk, increment the next largest page number.TLBPage TableDecimal 4669 2227 13916 34587 48870 12608 49225hex 0x123d 0x08b3 0x365c 0x871b 0xbee6 0x3140 0xc049Valid1110Index0123(a) For each access shown above, list456789abTagOxb0x70x30x4Valid100111010011▪ whether the access is a hit or miss in the TLB,▪ whether the access is a hit or miss in the page table,whether the access is a page fault,the updated state of the TLB.Physical PageNumber12469Time Since LastAccess4137Physical Page or in Disk5DiskDisk6911Disk4DiskDisk312(b) Repeat Part a, but this time use 16 KiB pages instead of 4 KiB pages. What would be some of the advantages of having a largerpage size? What are some of the disadvantages?

Name: As described in COD Section 5.7 (Virtual memory), virtual memory uses
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Description: As described in COD Section 5.7 (Virtual memory), virtual memory uses a page table to track the mapping of virtual addresses tophysical addresses. This exercise shows how this table must be updated as addresses are accessed. The following data const

Virtual memory is a computer memory management technique that provides an idealized abstraction of…

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As described in COD Section 5.7 (Virtual memory), virtual memory uses a page table to track the mapping of virtual addresses to physical addresses. This exercise shows how this table must be updated as addresses are accessed. The following data constitute a stream of virtual byte addresses as seen on a system. Assume 4 KiB pages, a four-entry fully associative TLB, and true LRU replacement. If pages must be brought in from disk, increment the next largest page number. Decimal 4669 hex TLB Page Table 2227 13916 34587 48870 12608 49225 0x123d 0x08b3 0x365c 0x871b Oxbee6 0x3140 0xc049 Valid 1 1 1 0 Index 0 (a) For each access shown above, list 123 4 5 6 7 8 9 a b Tag Oxb Ox7 0x3 0x4 Valid 1 0 0 1 1 1 0 1 0 0 1 1 ▪ whether the access is a hit or miss in the TLB, ▪ whether the access is a hit or miss in the page table, ▪ whether the access is a page fault, ▪ the updated state of the TLB. Physical Page Number 12 4 6 9 Time Since Last Access 4 1 3 7 Physical Page or in Disk 5 Disk Disk 6 9 11 Disk 4 Disk Disk 3 12 (b) Repeat Part a, but this time use 16 KiB pages instead of 4 KiB pages. What would be some of the advantages of having a larger page size? What are some of the disadvantages?

As described in COD Section 5.7 (Virtual memory), virtual memory uses a page table to track the mapping of virtual addresses to physical addresses. This exercise shows how this table must be updated as addresses are accessed. The following data constitute a stream of virtual byte addresses as seen on a system. Assume 4 KiB pages, a four-entry fully associative TLB, and true LRU replacement. If pages must be brought in from disk, increment the next largest page number. Decimal 4669 hex TLB Page Table 2227 13916 34587 48870 12608 49225 0x123d 0x08b3 0x365c 0x871b Oxbee6 0x3140 0xc049 Valid 1 1 1 0 Index 0 (a) For each access shown above, list 123 4 5 6 7 8 9 a b Tag Oxb Ox7 0x3 0x4 Valid 1 0 0 1 1 1 0 1 0 0 1 1 ▪ whether the access is a hit or miss in the TLB, ▪ whether the access is a hit or miss in the page table, ▪ whether the access is a page fault, ▪ the updated state of the TLB. Physical Page Number 12 4 6 9 Time Since Last Access 4 1 3 7 Physical Page or in Disk 5 Disk Disk 6 9 11 Disk 4 Disk Disk 3 12 (b) Repeat Part a, but this time use 16 KiB pages instead of 4 KiB pages. What would be some of the advantages of having a larger page size? What are some of the disadvantages?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Q3
Problem: A 1024 x 1024 array of 32-bit numbers is to be normalized as follows. For each column, the largest element is found and all elements of the column are divided by the value of this element. Assume that each page in the virtual memory consists of 4K bytes, and that 1M bytes of the main memory are allocated for storing array data during this computation. Assume that it takes 10 ms to load a page from the disk into the main memory when a page fault occurs. (a) Assume that the array is processed one column at a time. How many page faults would occur and how long does it take to complete the normalization process if the elements of the array are stored in column order in the virtual memory? (b) Repeat part (a) assuming the elements are stored in row order?