As described in COD Section 5.7 (Virtual memory), virtual memory uses a page table to track the mapping of virtual addresses tophysical addresses. This exercise shows how this table must be updated as addresses are accessed. The following data constitute astream of virtual byte addresses as seen on a system. Assume 4 KiB pages, a four-entry fully associative TLB, and true LRUreplacement. If pages must be brought in from disk, increment the next largest page number.TLBPage TableDecimal 4669 2227 13916 34587 48870 12608 49225hex 0x123d 0x08b3 0x365c 0x871b 0xbee6 0x3140 0xc049Valid1110Index0123(a) For each access shown above, list456789abTagOxb0x70x30x4Valid100111010011▪ whether the access is a hit or miss in the TLB,▪ whether the access is a hit or miss in the page table,whether the access is a page fault,the updated state of the TLB.Physical PageNumber12469Time Since LastAccess4137Physical Page or in Disk5DiskDisk6911Disk4DiskDisk312(b) Repeat Part a, but this time use 16 KiB pages instead of 4 KiB pages. What would be some of the advantages of having a largerpage size? What are some of the disadvantages?

Name: As described in COD Section 5.7 (Virtual memory), virtual memory uses
Uploaded: 2024-03-20T06:51:23.000Z
Channel: Bartleby
Description: As described in COD Section 5.7 (Virtual memory), virtual memory uses a page table to track the mapping of virtual addresses tophysical addresses. This exercise shows how this table must be updated as addresses are accessed. The following data const

Virtual memory is a computer memory management technique that provides an idealized abstraction of the storage resources that are actually available on a machine. It extends the available memory of a computer by using a combination of the physical RAM (Random Access Memory) and a portion of the hard disk or other secondary storage devices.The purpose of virtual memory is to allow applications to work with more memory than is physically installed on the computer, making it possible to run larger and more complex programs.The purpose of virtual memory is to allow applications to work with more memory than is physically installed on the computer, making it possible to run larger and more complex programs.Address Space:Each program running on a computer has its own address space. This address space is divided into smaller units called pages.Virtual Addresses:When a program requests memory or data, it uses virtual addresses. These virtual addresses are not directly associated with physical RAM.Memory Paging:The operating system, with the help of hardware, manages memory paging. Memory is divided into fixed-size blocks, typically called pages, and is transferred between RAM and a storage device in units of these pages. Pages that are currently in use or needed by a program are stored in RAM, while less frequently accessed or idle pages are swapped out to the disk.Page Table:A data structure called a page table is used to map virtual addresses to physical addresses. The page table keeps track of which pages of a program's address space are currently in RAM and which are on disk.Page Faults:When a program tries to access a page that is not in RAM (a page fault), the operating system fetches that page from the disk and places it in RAM. It may also decide to swap out another page from RAM to make space for the needed page.Please find the detailed answer below..The present TLB State.ValidTagPhysical Page NumberTime since Last Access10xc15110x814410x36210xb123The hit/miss of each page request.AddressTagHit/MissTag of VictimPage FaultPhysical Page0x123d0x1MISS0x4YES13(from Disk)0x08b30x0MISS0xbNO50x365c0x3HIT--NO60x871b0x8MISS0x7YES14(from Disk)0xbee60xbMISS0x1NO120x31400x3HIT--NO60xc0490xcMISS0x0YES15(from Disk)(b).AnswerAdvantages of virtual memoryinclude:Increased Application Space Isolation Efficient Memory Management Multi-TaskingIncreased Application Space:Virtual memory allows for larger and more complex programs to run, as they can use more memory than is physically available.Isolation:Each program runs in its own address space, which prevents one program from interfering with or corrupting the memory of another.Efficient Memory Management:Virtual memory allows the operating system to optimize memory usage by swapping pages in and out of RAM as needed.Multi-Tasking:Virtual memory enables a multitasking environment where multiple programs can run simultaneously without interfering with each other's memory.Disadvantage If the less number of pages having less efficient It store the less number of data in the page

Engineering

Computer Science

As described in COD Section 5.7 (Virtual memory), virtual memory uses a page table to track the mapping of virtual addresses to physical addresses. This exercise shows how this table must be updated as addresses are accessed. The following data constitute a stream of virtual byte addresses as seen on a system. Assume 4 KiB pages, a four-entry fully associative TLB, and true LRU replacement. If pages must be brought in from disk, increment the next largest page number. Decimal 4669 hex TLB Page Table 2227 13916 34587 48870 12608 49225 0x123d 0x08b3 0x365c 0x871b Oxbee6 0x3140 0xc049 Valid 1 1 1 0 Index 0 (a) For each access shown above, list 123 4 5 6 7 8 9 a b Tag Oxb Ox7 0x3 0x4 Valid 1 0 0 1 1 1 0 1 0 0 1 1 ▪ whether the access is a hit or miss in the TLB, ▪ whether the access is a hit or miss in the page table, ▪ whether the access is a page fault, ▪ the updated state of the TLB. Physical Page Number 12 4 6 9 Time Since Last Access 4 1 3 7 Physical Page or in Disk 5 Disk Disk 6 9 11 Disk 4 Disk Disk 3 12 (b) Repeat Part a, but this time use 16 KiB pages instead of 4 KiB pages. What would be some of the advantages of having a larger page size? What are some of the disadvantages?

As described in COD Section 5.7 (Virtual memory), virtual memory uses a page table to track the mapping of virtual addresses to physical addresses. This exercise shows how this table must be updated as addresses are accessed. The following data constitute a stream of virtual byte addresses as seen on a system. Assume 4 KiB pages, a four-entry fully associative TLB, and true LRU replacement. If pages must be brought in from disk, increment the next largest page number. Decimal 4669 hex TLB Page Table 2227 13916 34587 48870 12608 49225 0x123d 0x08b3 0x365c 0x871b Oxbee6 0x3140 0xc049 Valid 1 1 1 0 Index 0 (a) For each access shown above, list 123 4 5 6 7 8 9 a b Tag Oxb Ox7 0x3 0x4 Valid 1 0 0 1 1 1 0 1 0 0 1 1 ▪ whether the access is a hit or miss in the TLB, ▪ whether the access is a hit or miss in the page table, ▪ whether the access is a page fault, ▪ the updated state of the TLB. Physical Page Number 12 4 6 9 Time Since Last Access 4 1 3 7 Physical Page or in Disk 5 Disk Disk 6 9 11 Disk 4 Disk Disk 3 12 (b) Repeat Part a, but this time use 16 KiB pages instead of 4 KiB pages. What would be some of the advantages of having a larger page size? What are some of the disadvantages?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

What is the relationship between context switch time and interrupt latency?
1. Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses. 42, 137, 66, 50, 38, 225, 173, 22, 19, 88, 51, 43 a. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. b. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. Please explain the process.
Compare the main memory organization schemes of contiguous-memory allocation, pure segmentation, and pure paging with respect to the following issues: a. External fragmentation b. Internal fragmentation c. ability to share code across processes
Giventhe following assignment of some program’s virtual pages to physical pages in a system with 4 KiB byte pages, what physical memory address corresponds to virtual address 20000? (All values are given in decimal.)
#1#.
3
Suppose that a block is 1K Byte and that a disk address is 4 bytes. Suppose that files are implemented using i-nodes, and that an i-node has the following structure: the last address in the inode is a third-level indirect block; the second-to-last address is a second-level indirect block; the third-to-last address is an indirect block; and the remaining addresses are data blocks. Approximately how large a file can this system support?
Suppose a byte-addressable memory with 4 frames of size 8 bytes each and a paged virtual memory using a three-entry TLB. Suppose a process P has 8 pages of virtual memory space. Assume the following TLB and page table for process P: TLB Page Framell Framet Valid 1. 12 1. Page Table Assume process P generates a memory request with virtual address 0X3A. What is its corresponding physical address? You may represent the address in binary or hexadecimal notation (if hexadecimal notation, prefix with Ox). If the request causes a page fault, enter page fault.
5. A computer has an L1 and L2 cache, backed up by DRAM which is backed up by virtual memory. The TLB and L1 caches have hit times of .5 ns. The TLB's backup is the page table in DRAM while L1 cache's backup is an L2 cache. The L2 cache has a hit time of 1.5 ns. DRAM has a hit time of 10 ns. Swap space has a hit time of 2,500,000 ns. The hit rates are: TLB: 98.8%, L1: 91.5%, L2: 97.7%, DRAM: 99.9998% and swap space 100%. What is the effective access time?
Compare the main memory organization schemes of contiguous-memory allocation, pure segmentation, and pure paging with respect to the following issues: a. External fragmentation b. Internal fragmentation c. ability to share code across processes
Q3
Problem: A 1024 x 1024 array of 32-bit numbers is to be normalized as follows. For each column, the largest element is found and all elements of the column are divided by the value of this element. Assume that each page in the virtual memory consists of 4K bytes, and that 1M bytes of the main memory are allocated for storing array data during this computation. Assume that it takes 10 ms to load a page from the disk into the main memory when a page fault occurs. (a) Assume that the array is processed one column at a time. How many page faults would occur and how long does it take to complete the normalization process if the elements of the array are stored in column order in the virtual memory? (b) Repeat part (a) assuming the elements are stored in row order?