As described in COD Section 5.7 (Virtual memory), virtual memory uses a page table to track the mapping of virtual addresses to physical addresses. This exercise demonstrates how this table is updated as addresses are accessed. The following data represent a stream of virtual byte addresses as seen on a system. Assume 4 KiB pages, a four-entry fully associative TLB, and true LRU replacement. If pages must be brought in from disk, increment the next largest page number.### Decimal Addresses:- 4669- 2227- 13916- 34587- 48870- 12608- 49225### Hexadecimal Addresses:- 0x123d- 0x08b3- 0x365c- 0x871b- 0xbeee- 0x3140- 0xc049### TLB (Translation Lookaside Buffer):| Valid | Tag | Physical Page Number | Time Since Last Access ||-------|-----|-----------------------|------------------------|| 1 | 0xb | 12 | 4 || 1 | 0x7 | 4 | 1 || 1 | 0x3 | 6 | 3 || 0 | 0x4 | 9 | 7 |### Page Table:| Index | Valid | Physical Page or in Disk ||-------|-------|--------------------------|| 0 | 1 | 5 || 1 | 0 | Disk || 2 | 0 | Disk || 3 | 1 | 6 || 4 | 1 | 9 || 5 | 1 | 11 || 6 | 0 | Disk || 7 | 1 | 4 || 8 | 0 | Disk || 9 | 0 | Disk || 10 | 1 | 3 || 11 | 1 | 12 |### Tasks:(a) For each access shown above, list:- Whether the access is a hit or miss in the TLB.- Whether the access is a

In modern computer systems, efficient memory management is a critical aspect of ensuring optimal…

As described in COD Section 5.7 (Virtual memory), virtual memory uses a page table to track the mapping of virtual addresses to physical addresses. This exercise shows how this table must be updated as addresses are accessed. The following data constitute stream of virtual byte addresses as seen on a system. Assume 4 KiB pages, a four-entry fully associative TLB, and true LRU replacement. If pages must be brought in from disk, increment the next largest page number. TLB Page Table Decimal 4669 2227 13916 34587 48870 12608 49225 0x123d 0x08b3 0x365c 0x871b 0xbee6 0x3140 0xc049 hex Valid 1 1 1 0 Index 0 1 2345678 9 a Tag Oxb 0x7 0x3 0x4 Valid 1 0 0 1 1 1 0 1 0 0 1 Physical Page Number 12 4 6 9 Time Since Last Access 4 1 3 7 Physical Page or in Disk 5 Disk Disk 6 9 11 Disk 4 Disk Disk 3

As described in COD Section 5.7 (Virtual memory), virtual memory uses a page table to track the mapping of virtual addresses to physical addresses. This exercise shows how this table must be updated as addresses are accessed. The following data constitute stream of virtual byte addresses as seen on a system. Assume 4 KiB pages, a four-entry fully associative TLB, and true LRU replacement. If pages must be brought in from disk, increment the next largest page number. TLB Page Table Decimal 4669 2227 13916 34587 48870 12608 49225 0x123d 0x08b3 0x365c 0x871b 0xbee6 0x3140 0xc049 hex Valid 1 1 1 0 Index 0 1 2345678 9 a Tag Oxb 0x7 0x3 0x4 Valid 1 0 0 1 1 1 0 1 0 0 1 Physical Page Number 12 4 6 9 Time Since Last Access 4 1 3 7 Physical Page or in Disk 5 Disk Disk 6 9 11 Disk 4 Disk Disk 3

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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4.8 Consider a machine with a byte addressable main memory of 2" bytes and block size of 8 bytes. Assume that a dircct mapped cache consisting of 32 lines is used with this machine. a. How is a 16-bit memory address divided into tag, line number, and byte number? b. Into whal line would bytes with cach ofr the following addresses be stored? 0001 0001 0001 1011 1100 0011 0011 0100 1101 0000 0X01 1101 1010 1010 1010 1010 c. Suppose the byte with address 001 10100X001010isstored in the cache. What are the addresses of the other bytes stored along with it? d. How many total bytes of memory can he stored in the cache? e. Why is the tag also storecd in the cache?
1. Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses. 42, 137, 66, 50, 38, 225, 173, 22, 19, 88, 51, 43 a. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. b. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. Please explain the process.
Compare the main memory organization schemes of contiguous-memory allocation, pure segmentation, and pure paging with respect to the following issues: a. External fragmentation b. Internal fragmentation c. ability to share code across processes
Giventhe following assignment of some program’s virtual pages to physical pages in a system with 4 KiB byte pages, what physical memory address corresponds to virtual address 20000? (All values are given in decimal.)
#1#.
3
Suppose that a block is 1K Byte and that a disk address is 4 bytes. Suppose that files are implemented using i-nodes, and that an i-node has the following structure: the last address in the inode is a third-level indirect block; the second-to-last address is a second-level indirect block; the third-to-last address is an indirect block; and the remaining addresses are data blocks. Approximately how large a file can this system support?
Suppose a byte-addressable memory with 4 frames of size 8 bytes each and a paged virtual memory using a three-entry TLB. Suppose a process P has 8 pages of virtual memory space. Assume the following TLB and page table for process P: TLB Page Framell Framet Valid 1. 12 1. Page Table Assume process P generates a memory request with virtual address 0X3A. What is its corresponding physical address? You may represent the address in binary or hexadecimal notation (if hexadecimal notation, prefix with Ox). If the request causes a page fault, enter page fault.
5. A computer has an L1 and L2 cache, backed up by DRAM which is backed up by virtual memory. The TLB and L1 caches have hit times of .5 ns. The TLB's backup is the page table in DRAM while L1 cache's backup is an L2 cache. The L2 cache has a hit time of 1.5 ns. DRAM has a hit time of 10 ns. Swap space has a hit time of 2,500,000 ns. The hit rates are: TLB: 98.8%, L1: 91.5%, L2: 97.7%, DRAM: 99.9998% and swap space 100%. What is the effective access time?
Compare the main memory organization schemes of contiguous-memory allocation, pure segmentation, and pure paging with respect to the following issues: a. External fragmentation b. Internal fragmentation c. ability to share code across processes
Q3
Problem: A 1024 x 1024 array of 32-bit numbers is to be normalized as follows. For each column, the largest element is found and all elements of the column are divided by the value of this element. Assume that each page in the virtual memory consists of 4K bytes, and that 1M bytes of the main memory are allocated for storing array data during this computation. Assume that it takes 10 ms to load a page from the disk into the main memory when a page fault occurs. (a) Assume that the array is processed one column at a time. How many page faults would occur and how long does it take to complete the normalization process if the elements of the array are stored in column order in the virtual memory? (b) Repeat part (a) assuming the elements are stored in row order?