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The problems that follow will help reinforce your understanding of how caches work. Assume the following: · The memory is byte addressable. - Memory accesses are to 1-byte words (not to 4-byte words). · Addresses are 13 bits wide. · The cache is two-way set associative (E = 2), with a 4-byte block size (B = 4) and eight sets (S = 8). The contents of the cache are as follows, with all numbers given in hexadecimal notation. 2-way set associative cache Set Line O Line 1 Index Tag Vald Byte Byte Byte Byte Tag Vald Byte Byte Byte Byte O 1 2 3 O1 2 3 85 30 3F 10 - - - - 09 1 45 1 s0 ED 23 38 1 00 Bc 4F OB 37 |- - 08 - - - - 3 06 0 - - |- - |- 32 1 0s 78 12 AD 78 07 os os DE 18 48 sE 1. 05 70 05 1 40 67 C2 4 C7 38 5 71 - 1 OB 91 1 87 25 FO O - 6 AD 20 |- - - - DE 1 12 7 45 co 88 37 The following figure shows the format of an address (1 bit per box). Indicate (by labeling the diagram) the fields that would be used to determine the following: CO. The cache block offset CI. The cache set index CT. The cache tag 12 10 11 4

The problems that follow will help reinforce your understanding of how caches work. Assume the following: · The memory is byte addressable. - Memory accesses are to 1-byte words (not to 4-byte words). · Addresses are 13 bits wide. · The cache is two-way set associative (E = 2), with a 4-byte block size (B = 4) and eight sets (S = 8). The contents of the cache are as follows, with all numbers given in hexadecimal notation. 2-way set associative cache Set Line O Line 1 Index Tag Vald Byte Byte Byte Byte Tag Vald Byte Byte Byte Byte O 1 2 3 O1 2 3 85 30 3F 10 - - - - 09 1 45 1 s0 ED 23 38 1 00 Bc 4F OB 37 |- - 08 - - - - 3 06 0 - - |- - |- 32 1 0s 78 12 AD 78 07 os os DE 18 48 sE 1. 05 70 05 1 40 67 C2 4 C7 38 5 71 - 1 OB 91 1 87 25 FO O - 6 AD 20 |- - - - DE 1 12 7 45 co 88 37 The following figure shows the format of an address (1 bit per box). Indicate (by labeling the diagram) the fields that would be used to determine the following: CO. The cache block offset CI. The cache set index CT. The cache tag 12 10 11 4

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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This problem concerns the cache in Attached problem 
A. List all of the hex memory addresses that will hit in set 2.
B. List all of the hex memory addresses that will hit in set 4.
C. List all of the hex memory addresses that will hit in set 5.
D. List all of the hex memory addresses that will hit in set 7.

The problems that follow will help reinforce your understanding of how caches work. Assume the following: · The memory is byte addressable. - Memory accesses are to 1-byte words (not to 4-byte words). · Addresses are 13 bits wide. · The cache is two-way set associative (E = 2), with a 4-byte block size (B = 4) and eight sets (S = 8). The contents of the cache are as follows, with all numbers given in hexadecimal notation. 2-way set associative cache Set Line O Line 1 Index Tag Vald Byte Byte Byte Byte Tag Vald Byte Byte Byte Byte O 1 2 3 O1 2 3 85 30 3F 10 - - - - 09 1 45 1 s0 ED 23 38 1 00 Bc 4F OB 37 |- - 08 - - - - 3 06 0 - - |- - |- 32 1 0s 78 12 AD 78 07 os os DE 18 48 sE 1. 05 70 05 1 40 67 C2 4 C7 38 5 71 - 1 OB 91 1 87 25 FO O - 6 AD 20 |- - - - DE 1 12 7 45 co 88 37 The following figure shows the format of an address (1 bit per box). Indicate (by labeling the diagram) the fields that would be used to determine the following: CO. The cache block offset CI. The cache set index CT. The cache tag 12 10 11 4
Transcribed Image Text:The problems that follow will help reinforce your understanding of how caches work. Assume the following: · The memory is byte addressable. - Memory accesses are to 1-byte words (not to 4-byte words). · Addresses are 13 bits wide. · The cache is two-way set associative (E = 2), with a 4-byte block size (B = 4) and eight sets (S = 8). The contents of the cache are as follows, with all numbers given in hexadecimal notation. 2-way set associative cache Set Line O Line 1 Index Tag Vald Byte Byte Byte Byte Tag Vald Byte Byte Byte Byte O 1 2 3 O1 2 3 85 30 3F 10 - - - - 09 1 45 1 s0 ED 23 38 1 00 Bc 4F OB 37 |- - 08 - - - - 3 06 0 - - |- - |- 32 1 0s 78 12 AD 78 07 os os DE 18 48 sE 1. 05 70 05 1 40 67 C2 4 C7 38 5 71 - 1 OB 91 1 87 25 FO O - 6 AD 20 |- - - - DE 1 12 7 45 co 88 37 The following figure shows the format of an address (1 bit per box). Indicate (by labeling the diagram) the fields that would be used to determine the following: CO. The cache block offset CI. The cache set index CT. The cache tag 12 10 11 4
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