In the space below list the sequence of processes in the execution order that are on the critical path for the swi instruction. (Processes to choose from are: Register Read, Register Write, Memory Read, Memory Write, ALU1, ALU2, MuxALUSrc1, MUXALUSrc2, MuxALUSrc3, SignExtension, Instruction Memory, Add). What is the minimum cycle time needed to execute this instruction?
In the space below list the sequence of processes in the execution order that are on the critical path for the swi instruction. (Processes to choose from are: Register Read, Register Write, Memory Read, Memory Write, ALU1, ALU2, MuxALUSrc1, MUXALUSrc2, MuxALUSrc3, SignExtension, Instruction Memory, Add). What is the minimum cycle time needed to execute this instruction?
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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Question
![Quiz 5: In this problem we want to set the control signals of the datapath shown
below (also in in slide # 1 of "chapter3_single_cycle_datapaths.pptx") so that it
supports execution of a new instruction called swi.
Single Cycle Datapath:
PC
Read Instru-
address
ction
[31-0]
Instruction
memory
Sns
Add
Ins
1 [25-21]
1 [20-16]
[15-11].
1[10-0]
RegWrite
Read
register 1
Read
register 2
Write
register
Write
data
Read
data 1
Read
data 2
Read Ins
Write 3ns
Sign
extend
2ns
MemWrite
Read Read
address data
Write
address
Read Gns
Write
data Write 10ns
ins
ALUSTO1
MemRead
ALU
Result
2ns
ALUOP1
-XEWO)
ins
ALUSrc2
ALUSrc3
x=3
ins
ALU
Result
2ns
ALUOP2
swi rd, rs, rt, imm # Memory [R[rs]]= R[rt],
R[rd] =R [rs]+R [rt]+Imm
#this instruction copies contents of "rt" register into the
main memory addressed by the "rs" register. In the same cycle
it add "rs" and "rt" register contents along with the "imm"
field of the instruction and writes the final result into the
"rd" register.
You are NOT allowed to modify the datapath. ALU operation (ALUOP) can be add,
sub, mul, sll, and srl. Indicate the value of each control signal (RegWrite, ALUSrc1,
ALUSrc2, ALUSrc3, ALUOp1, ALUOp2, MemRead, MemWrite). You must use "X" for
control signals when applicable.
In the space below list the sequence of processes in the execution order that are on
the critical path for the swi instruction. (Processes to choose from are: Register Read,
Register Write, Memory Read, Memory Write, ALU1, ALU2, MuxALUSrc1,
MUXALUSrc2, MuxALUSrc3, SignExtension, Instruction Memory, Add). What is the
minimum cycle time needed to execute this instruction?](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F5ecf1484-f95f-4119-9858-43c8382b92c0%2F52c5b112-3453-4dab-9ce5-0be54b5984fd%2F57lavyk_processed.jpeg&w=3840&q=75)
Transcribed Image Text:Quiz 5: In this problem we want to set the control signals of the datapath shown
below (also in in slide # 1 of "chapter3_single_cycle_datapaths.pptx") so that it
supports execution of a new instruction called swi.
Single Cycle Datapath:
PC
Read Instru-
address
ction
[31-0]
Instruction
memory
Sns
Add
Ins
1 [25-21]
1 [20-16]
[15-11].
1[10-0]
RegWrite
Read
register 1
Read
register 2
Write
register
Write
data
Read
data 1
Read
data 2
Read Ins
Write 3ns
Sign
extend
2ns
MemWrite
Read Read
address data
Write
address
Read Gns
Write
data Write 10ns
ins
ALUSTO1
MemRead
ALU
Result
2ns
ALUOP1
-XEWO)
ins
ALUSrc2
ALUSrc3
x=3
ins
ALU
Result
2ns
ALUOP2
swi rd, rs, rt, imm # Memory [R[rs]]= R[rt],
R[rd] =R [rs]+R [rt]+Imm
#this instruction copies contents of "rt" register into the
main memory addressed by the "rs" register. In the same cycle
it add "rs" and "rt" register contents along with the "imm"
field of the instruction and writes the final result into the
"rd" register.
You are NOT allowed to modify the datapath. ALU operation (ALUOP) can be add,
sub, mul, sll, and srl. Indicate the value of each control signal (RegWrite, ALUSrc1,
ALUSrc2, ALUSrc3, ALUOp1, ALUOp2, MemRead, MemWrite). You must use "X" for
control signals when applicable.
In the space below list the sequence of processes in the execution order that are on
the critical path for the swi instruction. (Processes to choose from are: Register Read,
Register Write, Memory Read, Memory Write, ALU1, ALU2, MuxALUSrc1,
MUXALUSrc2, MuxALUSrc3, SignExtension, Instruction Memory, Add). What is the
minimum cycle time needed to execute this instruction?
Expert Solution

Step 1 Introduction
Single Cycle Datapath which refers to the equivalent to the original single cycle datapath. The data memory which has only one Address input. The actual memory operation that can be determined from the MemRead and MemWrite control in the signals. There are separate memories that are used for the instructions and the data.
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