Q2. For the following assume that values A, B, C, D, E, and F reside in memory. Also assumethat instruction operation codes are represented in 6 bits, memory addresses are 64 bits, datasize is 32 bits and register addresses are 5 bits.a. For each instruction set architecture shown in Figure A.1, how manyaddresses or names (including both memory and register), appear in each instructionfor the code to compute C = A+ B, and what is the total code size?passorTOSMemory(A)Accumulator (C) Registry (D) Reloed ooreFigure A.1 Operand locations for four instruction set architecture classes. The arrows indicate whether the operand is an input or the result of the orithmetic-logical unit ALU operation, or both an input and result Lighter shoesindicate inputs, and the dark shode indicates the result in a top of stack (TOS) register points to the top inputoperand, which is combined with the operand below. The first operand is removed from the stack, the result takes theplace of the second operand, and 105 is updated to point to the result AB operands are impliotin (BL, the accumulator is both an implict input operand and a result, in KL ene input operand is a register, one is in memoryand the result goes to a register All operands are registers in ) and, like the stack architecture, can be transferredto memory only via spaute intruction push or pop for (A) and load or store for DStackPush AlPush BAddPop CAccumulatorLoad AAdd B.Store CDestroyed operandRegister(register-memory)Load R1, AAdd R3, R1,8Store R3.CFigure A.2 The code sequence for C=A+B for four classes of instruction sets. Notethat the Add instruction has implicit operands for stack and accumulator architecturesand explicit operands for register architectures. It is assumed that A, B, and Call belongin memory and that the values of A and B cannot be destroyed. Figure A.1 shows theAdd operation for each class of architecture.b. Some of the instruction set architectures in Figure A.1 destroy operands in the courseof computation. This loss of data values from processor internal storage hasperformance consequences. For each architecture in Figure A.2, write the codesequence to compute:C = A + BD=A+FE = C + DOverheadinstruction?Register(load-store)Load R1,ALoad R2, BAdd R3, R1, R2Store R3, CIn your code, mark each operand that is destroyed during execution and mark each"overhead" instruction that is included just to overcome this loss of data from processorinternal storage. What is the total code size, the number of bytes of instructions and datamoved to or from memory, the number of overhead instructions, and the number ofoverhead data bytes for each of your code sequences? You may use a table like this toshow your results:CodeCode sizeSize of data movedto/from memory

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Q2. For the following assume that values A, B, C, D, E, and F reside in memory. Also assume that instruction operation codes are represented in 6 bits, memory addresses are 64 bits, data size is 32 bits and register addresses are 5 bits. a. For each instruction set architecture shown in Figure A.1, how many addresses or names (including both memory and register), appear in each instruction for the code to compute C = A+ B, and what is the total code size? P TOS My (A) (C) R (D) Figure A.1 Operand locations for four instruction set architecture classes. The arrows indicate whether the oper and is an input or the result of the orithmetic logical unit ALU operation, or both an input and rightshades indicate inputs, and the dark shode indicates the result in (A) a top of stack (TOS) register points to the top input operand, which is combined with the operand below. The fint operand is removed from the stack, the the place of the second operand, and 105 is upted to point to the result AB operands are implct in (BL, the accu mulator is both an implat inpat eperand and a result, in KL ene input operand is a register, one is in memory and the rest goes to register Al operands are register in and, ike the stack architecture, can be transfe to memory only via spate intruction push or pep for (A) and load or store for D Stack Push A Push B Add Pop C Accumulator Load A Add B Store C Destroyed operand Register (register-memory) Load R1, A Add R3, R1,8 Store R3.C Register (load-store) Figure A.2 The code sequence for C=A+B for four classes of instruction sets. Note that the Add instruction has implicit operands for stack and accumulator architectures and explicit operands for register architectures. It is assumed that A, B, and Call belong in memory and that the values of A and B cannot be destroyed. Figure A.1 shows the Add operation for each class of architecture. b. Some of the instruction set architectures in Figure A. 1 destroy operands in the course of computation. This loss of data values from processor internal storage has performance consequences. For each architecture in Figure A.2, write the code sequence to compute: C = A + B D=A+F Overhead instruction? Load R1,A Load R2,B Add R3, R1, R2 Store R3,C E = C + D In your code, mark each operand that is destroyed during execution and mark each "overhead" instruction that is included just to overcome this loss of data from processor internal storage. What is the total code size, the number of bytes of instructions and data moved to or from memory, the number of overhead instructions, and the number of overhead data bytes for each of your code sequences? You may use a table like this to show your results: Code Code size Size of data moved to/from memory