(b) In a two-level cache system, it is known that a program has 1000 instructions with memory references, of which 40 misses occur in the first level cache and 10 misses in the second level cache. Calculate the local miss rate for each level of the cache, and give the global cache miss rate of the cache system.

(b) In a two-level cache system, it is known that a program has 1000 instructions with memory references, of which 40 misses occur in the first level cache and 10 misses in the second level cache. Calculate the local miss rate for each level of the cache, and give the global cache miss rate of the cache system.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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5. suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each cache block contains 64 bytes. a) how many blocks of main memory are there? b) what is the format of a memory address as seen by the cache ; that is, what are the size of the tag and offset field. c) To which cache block will the memory address 0x01D872 map?
4. Assume 32 bit memory addresses, which are byte addresses. You have a direct-mapped cache with a block size of 8 bytes, and a size of 128 blocks. How many bits will the index, block offset, and tag be? How many total bits are required for the cache, including the data?
Please help with detailed explanation for problem C, don't copy solutions from other sources. Consider a byte addressing architecture with 64-bit memory addresses. a)Which bits of the address would be used in the tag, index and offset in a direct-mapped cache with 512 1-word blocks. b)Which bits of the address would be used in the tag, index and offset in a direct-mapped cache with 64 8-word blocks. c)What is the ratio of bits used for storing data to total bits stored in the cache in each of the above cases a and b?
For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. a. What is the cache block size in words? b. How many entries does the cache have? Tag 31-13 Index 12-6 Offset 5-0
A 2-way set associative cache consists of four sets. Main memory contains 2K blocks of eight words each. Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes. Compute the hit ratio for a program that loops 6 times from locations 8 to 51 in main memory. You may leave the hit ratio in terms of a fraction. Please show details how you obtain the result.
This problem concerns the cache in Attached problem A. List all of the hex memory addresses that will hit in set 2.B. List all of the hex memory addresses that will hit in set 4.C. List all of the hex memory addresses that will hit in set 5.D. List all of the hex memory addresses that will hit in set 7.
In designing a computer’s cache system, the cache block or cache line size is an important parameter. Which of the following statements is correct in this context? A smaller block size implies better spatial locality A smaller block size implies a smaller cache tag and hence lower cache tag overhead A smaller block size implies a larger cache tag and hence lower cache hit time A smaller bock size incurs a lower cache miss penalty
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A computer of 32 bits has a cache memory of 64 KB with a cache line size of 64 bytes. The cache access time is 20 ns, and the miss penalty is 120 ns. The cache is 2-way associative. a) What is the number of cache lines? b) What is the number of cache sets? c) What is the number of lines per set? d) Draw a scheme of this cache. e) Calculate the time to read a word in case of miss.
A computer is using a fully associative cache and has 216 bytes of main memory (byte addressable) and a cache of 64 blocks, where each block contains 32 bytes. a. How many blocks of main memory are there? b. What will be the sizes of the tag, index, and byte offset fields? c. To which cache set will the memory address 0xF8C9(hexadecimal) map?
3. The table below represents five lines from a cache that uses fully associative mapping with a block size of 8. Identify the address of the shaded data, 0xE6, first in binary and then in hexadecimal. The tag numbers and word id bits are in binary, but the content of the cache (the data) is in hexadecimal. Word id bits Tag 000 001 010 011 100 101 110 111 ------------------------------------------ 1011010 10 65 BA 0F C4 19 6E C3 1100101 21 76 CB 80 D5 2A 7F B5 0011011 32 87 DC 91 E6 3B F0 A6 1100000 43 98 ED A2 F7 4C E1 97 1111100 54 9A FE B3 08 5D D2 88