In a two-level cache sysle of L and L caches are I and 8 clock cycles, rpectively. The miss peralny from the La cache to main oory is 1 cck cycles. The miss rale of L cacle is twice that of La The average eory access tame (AMAT) of this cacle system 2 cycles The miss rates of L dla tespectively are.

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
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In a teo-level cache system, tie access times
of L and Le caches are I and 8 clock cycles,
rapectavely. The miss penaity from the La
cacle to main roory is 18 clock cycles. The
miss rate of Li cache is twice that of La The
average emory access Latme (AMAT) of this
cacle system is
2 cycles The mias rates of L
and L tespectively are:
Transcribed Image Text:In a teo-level cache system, tie access times of L and Le caches are I and 8 clock cycles, rapectavely. The miss penaity from the La cacle to main roory is 18 clock cycles. The miss rate of Li cache is twice that of La The average emory access Latme (AMAT) of this cacle system is 2 cycles The mias rates of L and L tespectively are:
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