The low order 4 bits of the address indicate location in the cache line and the next 4 bits indicate which line in the cache should be used and the remaining bits of the address are used as the cache tag. If the following addresses are read in this order, indicate (circle or similar) each one that would result in a cache miss. 2A1220: Miss first time is always a cache miss 2A122C: Cache Hit, same line B14408: Miss, cache line changed B14428: Hit, the cache line is the same 2A122C: Miss would again occur 2 consider the previous problem using a fully associative cache. Assume the same cache lines are initially in the cache. Does this change the answer from the previous problem? If so, how? If not, why not?

The low order 4 bits of the address indicate location in the cache line and the next 4 bits indicate which line in the cache should be used and the remaining bits of the address are used as the cache tag. If the following addresses are read in this order, indicate (circle or similar) each one that would result in a cache miss. 2A1220: Miss first time is always a cache miss 2A122C: Cache Hit, same line B14408: Miss, cache line changed B14428: Hit, the cache line is the same 2A122C: Miss would again occur 2 consider the previous problem using a fully associative cache. Assume the same cache lines are initially in the cache. Does this change the answer from the previous problem? If so, how? If not, why not?

Computer Networking: A Top-Down Approach (7th Edition)

7th Edition

ISBN:9780133594140

Author:James Kurose, Keith Ross

Publisher:James Kurose, Keith Ross

Chapter1: Computer Networks And The Internet

Section: Chapter Questions

Problem R1RQ: What is the difference between a host and an end system? List several different types of end...

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Question

1
The low order 4 bits of the address indicate location in the cache line and the next 4
bits indicate which line in the cache should be used and the remaining bits of the
address are used as the cache tag.
If the following addresses are read in this order, indicate (circle or similar) each one that
would result in a cache miss.
2A1220: Miss first time is always a cache miss
2A122C: Cache Hit, same line
B14408: Miss, cache line changed
B14428: Hit, the cache line is the same
2A122C: Miss would again occur
2
consider the previous problem using a fully associative cache.
Assume the same cache lines are initially in the cache.
Does this change the answer from the previous problem?
If so, how?
If not, why not?

Consider the previous problem using a fully associative cache.
Assume the same cache lines are initially in the cache.
Does this change the answer from the previous problem?
If so, how?
If not, why not?

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The low order 4 bits of the address indicate location in the cache line and the next 4 bits indicate which line in the cache should be used and the remaining bits of the address are used as the cache tag. If the following addresses are read in this order, indicate (circle or similar) each one that would result in a cache miss. 2A1220 2A122C B14408 B14428 2A122C