5 32 bits in bc r has latency has latency the hit latenci associative
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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![Consider two cache organizations. The first one
is 64 kB way associative with 64 byte block size.
The second one is of the 64 kB direct mapped
cache. The size of an address is 32 bits in both
organization. A 4 to 1 multiplexer has latency of
0.8 ns which k bit comparator has latency of
k/5 nsec. The difference between the hit latencies
of both cache organization (i.e. associative hit
latency – direct mapped hit latency) (in nsec)
is_](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F592cc228-aa5f-4fce-9da8-594496adbffa%2F58140661-5f1c-4276-b910-347da8b0b489%2F4uevq3u_processed.jpeg&w=3840&q=75)
Transcribed Image Text:Consider two cache organizations. The first one
is 64 kB way associative with 64 byte block size.
The second one is of the 64 kB direct mapped
cache. The size of an address is 32 bits in both
organization. A 4 to 1 multiplexer has latency of
0.8 ns which k bit comparator has latency of
k/5 nsec. The difference between the hit latencies
of both cache organization (i.e. associative hit
latency – direct mapped hit latency) (in nsec)
is_
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