Some portion of cache system B represented a 2way set-associative mapping cache system.The system is byte-addressable and the block site is one word (4 bytesl The tag and set number are represented with a binary numbers. The contents of words in theblock are mpreserted with headecimalTagSet NumberWord within blockbo0110ho s000 0100 10010110 110111 1100 0100 1001p110 110172s0 1000 0100 10010110111011 1100 0100 110s0110 1110ho 1000 0100 100120t1100 0100 100101101111to to00 os00 soon100000110sb1110000boiooo sesboso3. f we request memory read from memory address F1 35 C3, what data do we read?4 we request memory read from memory address A1 25 BA, what data do we read?S.H we access memory as the following order in cache system 8A1 FF 8881 FF B8AL FF B8B1 FF BAS FF 61FF BRhow many cache ie would ocou for the data ret

Some portion of cache system B represented a 2 way set-associative mapping cache system. The system is byte-addressable and the block size is one word (4 bytes. The tag and set number are represented with a birary numbers. The contents of words in the block are mpresented with headecimal Tag Set Nuimber Word within block 01 10 bo s000 0100 1001 01101101 1 11000100 1001 b110 1101 32 to 1000 0100 1001 b110 1110 1100 0100 1101 b1101110 bo s000 0s00 1001 e110 1111 b1101111 ho 1000 000 s00n p10000 10000010 b1110000 ss10001 voei onto a1.0010 8.

Some portion of cache system B represented a 2 way set-associative mapping cache system. The system is byte-addressable and the block size is one word (4 bytes. The tag and set number are represented with a birary numbers. The contents of words in the block are mpresented with headecimal Tag Set Nuimber Word within block 01 10 bo s000 0100 1001 01101101 1 11000100 1001 b110 1101 32 to 1000 0100 1001 b110 1110 1100 0100 1101 b1101110 bo s000 0s00 1001 e110 1111 b1101111 ho 1000 000 s00n p10000 10000010 b1110000 ss10001 voei onto a1.0010 8.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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In a Direct Mapped Cache Memory Physical Address format the Cache line offset field size and word offset field size are same (with word size of one Byte). The number of tag bits in the Physical Address format is equal to the number of blocks in Cache Memory. If the Tag field Size is Mega words. 16 bits, the size of the physical Memory is
In a certain computer, the virtual addresses are 32 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 16 kB and the word size is 2 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 64 valid entries. Hit ratio of TLB is 100% then maximum number of distinct virtual addresses that can be translated is K.
Assume the address format for a fully-associative cache is as follows: 6 bits 2 bits Tag Offset 8 bits Given the cache directory is as shown in the diagram below, indicate whether the memory reference Ox5E results in a cache hits or a miss. Tag valid Block 000 110110 001 000001 010 000010 011 000101 100 001000 1 101 100010 110 010111 111 110110 O Hit O Miss
We are given a list of 64-bit memory address references, given as word addresses. Ox03, Oxb4, Ox2b, Ox02, Oxbf, Ox58, Oxbe, Ox0e, Oxb5, 0x2c, Oxba, Oxfd (A) For each of these references, identify the binary word address, the tag, and the index given a direct-mapped cache with 16 one- word blocks. Also list whether each reference is a hit or a miss, assuming the cache is initially empty. (B) For each of these references, identify the binary word address, the tag, the index, and the offset given a direct-mapped cache with two-word blocks and a total size of eight blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. (C) You are asked to optimize a cache design for the given references (i.e. addresses). There are three direct-mapped cache designs possible, all with a total of eight words of data: (i) Cache1 has 1-word blocks, (ii) Cache2 has 2-word blocks, and (iii) Cache3 has 4-word blocks.
For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. a. What is the cache block size in words? b. How many entries does the cache have? Tag 31-13 Index 12-6 Offset 5-0
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A 2-way set associative cache consists of four sets. Main memory contains 2K blocks of eight words each. Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes. Compute the hit ratio for a program that loops 6 times from locations 8 to 51 in main memory. You may leave the hit ratio in terms of a fraction. Please show details how you obtain the result.
A computer of 32 bits has a cache memory of 64 KB with a cache line size of 64 bytes. The cache access time is 20 ns, and the miss penalty is 120 ns. The cache is 2-way associative. a) What is the number of cache lines? b) What is the number of cache sets? c) What is the number of lines per set? d) Draw a scheme of this cache. e) Calculate the time to read a word in case of miss.
Below is a series of byte addresses in a system with 32 bit words. Assuming a direct-mapped cache with 4-word blocks and a total size of 32 words that is initially empty, (a) label each reference in the list as a hit or a miss and (b) show the entire history of the cache, including tag and data. Byte Address Byte Address (Hexadecimal) (Binary) Hit/Miss 76 0000 0000 0111 0110 1E3 0000 0001 1110 0011 815 0000 1000 0001 0101 141 0000 0001 0100 0001 170 0000 0001 0111 0000 5E1 0000 0101 1110 0001 320 0000 0011 0010 1100 B10 0000 1011 0001 0000 175 0000 0001 0111 0101 583 0000 0101 1000 0011 1FF 0000 0001 1111 1111 7A 0000 0000 0111 1010 2B2 0000 0010 1011 0010 5E4 0000 0101 1110 0100 816 0000 1000 0001 0110 438 0000 0100 0011 1000
3. The table below represents five lines from a cache that uses fully associative mapping with a block size of 8. Identify the address of the shaded data, 0xE6, first in binary and then in hexadecimal. The tag numbers and word id bits are in binary, but the content of the cache (the data) is in hexadecimal. Word id bits Tag 000 001 010 011 100 101 110 111 ------------------------------------------ 1011010 10 65 BA 0F C4 19 6E C3 1100101 21 76 CB 80 D5 2A 7F B5 0011011 32 87 DC 91 E6 3B F0 A6 1100000 43 98 ED A2 F7 4C E1 97 1111100 54 9A FE B3 08 5D D2 88
The low order 4 bits of the address indicate location in the cache line and the next 4 bits indicate which line in the cache should be used and the remaining bits of the address are used as the cache tag. If the following addresses are read in this order, indicate (circle or similar) each one that would result in a cache miss. 2A1220 2A122C B14408 B14428 2A122C
Given an 8-word, 4-way set associative cache, and the sequence of address accesses below, enter the number of misses. 22 24 22 13 13 22