Ina kwy set asociative cache, the cache livided inte v s, of which comists o lines The lines of a set we placed sequence one afler another The lines is aet are sequenced before the ines in set (sti The main memory blocks are sunted ands. The main memey block nanbered ust be mapped to any one of the cache lines w rom
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- s The ain memory of a computer has 2e m ocks while the cache has 2 hocks If the cache uses the set asociative mapping scheme with 2 blocks per set, then block k of the main memory maps to the setA two-level cache hierarchy of L1 and L2 with 2 and 3 blocks respectively is designed. Both L1 and L2 are fully-associative with LRU replacement policy. A sequence of references (block addresses from left to right, denoted as letters) is given in the table. Both caches are empty initially. You need to simulate the contents of L1 and L2 for the given sequence. Note that each request goes to L1 first. A request is issued to L2 only if it misses L1. In case of a L2 hit, the requested block is fetched from L2 and placed into L1, both in the MRU position. In case of a L2 miss, the block is loaded from memory into both L1 and L2 caches in the MRU position. The cache contents are displayed by the block addresses from MRU position to LRU position, separated by a comma.“Prefetching” is a technique that leverages predictable address patterns to speculatively bring in additional cache blocks when a particular cache block is accessed. One example of prefetching is a stream buff er that prefetches sequentially adjacent cache blocks into a separate buff er when a particular cache block is brought in. If the data is found in the prefetch buff er, it is considered as a hit and moved into the cache and the next cache block is prefetched. Assume a two-entry stream buff er and assume that the cache latency is such that a cache block can be loaded before the computation on the previous cache block is completed. What is the miss rate for the address stream above?Cache block size (B) can aff ect both miss rate and miss latency. Assuming a 1-CPI machine with an average of 1.35 references (both instruction and data) per instruction, help find the optimal block size given the following miss rates for various block sizes. 8: 4% 16: 3% 32: 2% 64: 1.5% 128: 1%…
- Match each type of miss with its definition. Compulsory Miss Capacity Miss Conflict Miss ✓ [Choose ] A miss that occurs because this is the first time we have accessed the block that contains the desired value A miss that occurs because the values that we are working on both map to the same place in the cache and therefore can't both A miss that occurs because we are unable to fit all of the values that we are working on inside the cache [Choose ]31 tn a twe-level cache system, the access times of L and la cche are I and ckek cycles, espectively. The mies penalty bum the La cache to mein memory is IR clock cycles. The miss rate of L cache is twike that of La The avermge memory eess tine (AMAT) of this Cnele system is 2 cycles. The mi rates of L and La respeetively areIn a teo-level cache system, tie access times of L and Le caches are I and 8 clock cycles, rapectavely. The miss penaity from the La cacle to main roory is 18 clock cycles. The miss rate of Li cache is twice that of La The average emory access Latme (AMAT) of this cacle system is 2 cycles The mias rates of L and L tespectively are:
- Consider a fully-associative cache of size 4. Each slot in the cache can have just one item (i.e. the line size is 1 item). The cache is empty to start with. The cache uses an LRU replacement policy: every slot has a counter; every time a slot is accessed, a global counter is incremented and the value is stored in the slot counter; the slot with the lowest counter value is chosen for replacement. Sequence Id 1 2 3 4 5 6 7 8 10 Address Ox0012 0x0014 Ox0016 Ox0018 0x0016 0x0012 0x0020 Ox0022 0x0014 Ox0012 Hit/Miss Accesses 1 to 10 are respectively: Select one: O a. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Miss, Miss O b. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Hit, Hit O. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Hit, Miss O d. Miss, Miss, Miss, Miss, Hit, Miss, Miss, Miss, Miss, Hit O e. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Miss, HitWrite a C program that implements FIFO and LRU page-replacement algorithms. The code should take in only one command line argument, which will be the filename of the input file which contains a page-reference sequence. The output of the program should print the same information as the images attached. NOTE: the resulting cache state is kept in their respective orders.Given a computer with a memory system having a40_bit address, a cache consisting of 8192 blocks each is 32 words. For the following cache types: Direct Mapped (DM), Fully_ associative (FA), Two_way set associative (2_way), Four_way set associative (4_way), Eight_way set associative (8_way), calculate the following values as specified. (Use paper and pencil to do needed calculations and write only the final answer in the given blank space). 1) DM: The size of the index field = Blank 1bits 2) 2_way: The size of the index field =Blank 2bits 3) 4_way: The size of the index field =Blank 3bits 4) 8_way: The size of the index field =Blank 4bits 5) The size of the offset field = Blank 5bits 6) DM: The size of the tag field =Blank 6bits 7) 2_way: The size of the tag field =Blank 7bits 8) 4_way: The size of the tag field =Blank 8bits 9) 8_way: The size of the tag field =Blank 9bits 10) FA: The size of the tag field =Blank 10bits
- Caches are important to providing a high-performance memory hierarchy toprocessors. Below is a list of 32-bit memory address references, given as word addresses.4, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253 a. For each of these references, identify the binary address, the tag, and the indexgiven a direct-mapped cache with 16 one-word blocks. Also list if each reference is a hitor a miss, assuming the cache is initially empty.b. For each of these references, identify the binary address, the tag, and the indexgiven a direct-mapped cache with two-word blocks and a total size of 8 blocks. Also listif each reference is a hit or a miss, assuming the cache is initially empty.We are given a list of 64-bit memory address references, given as word addresses. Ox03, Oxb4, Ox2b, 0x02, Oxbf, Ox58, Oxbe, 0x0e, Oxb5, Ox2c, Oxba, Oxfd (A) For each of these references, identify the binary word address, the tag, and the index given a direct-mapped cache with 16 one-word blocks. Also list whether each reference is a hit or a miss, assuming the cache is initially empty. (B) For each of these references, identify the binary word address, the tag, the index, and the offset given a direct-mapped cache with two- word blocks and a total size of eight blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. (C) You are asked to optimize a cache design for the given references (i.e. addresses). There are three direct-mapped cache designs possible, all with a total of eight words of data: (i) Cache1 has 1-word blocks, (ii) Cache2 has 2-word blocks, and (iii) Cache3 has 4-word blocks.2-Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses. a. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with two-word blocks and a total size of 4 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. 42, 180, 46, 185, 189, 3, 181, 43, 6, 189, 65, 190 b. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with four-word blocks and a total size of 4 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. c. For each of these references, identify the binary address, the tag, and the index given a two way associative cache with two-word blocks and a total size of 4 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty d. For each of these…