13. T F In a mirrored array, each disk stores exactly the same data. 14. T F Write back in cache coherency writes data back to main memory immediately upon a change in the cache.
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![13. T F In a mirrored array, each disk stores exactly the same data.
14. T F Write back in cache coherency writes data back to main memory immediately upon
a change in the cache.](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F72793f1c-49a4-45c4-aee2-452bd22a186e%2Fb7ca6d20-5f19-4f74-9cf5-2a15c815f31d%2Fbu75uuz_processed.png&w=3840&q=75)
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- Q4) A computer has an 8 GByte memory with 64 bit word sizes. Each block of memory stores 16 words. The computer has a direct-mapped cache of 128 blocks. The computer uses word level addressing. What is the address format? If we change the cache to a 4- way set associative cache, what is the new address format?Homework 2 Note: This homework is for topics covered in Chapter 2. You do NOT have to submit it. 1. If the number of bits in the memory address is 7 bits, what is the maximum memory size? 2. True or False a. A typical memory hierarchy starts with a small, cheap, and relatively slow module, called the cache () b. A byte has 4 bits () section: 3. Place the following commands in the (POP, ROTATE, RETURN, SHIFT, AND, INCREMENT) proper Data Movement Arithmetic and Sequencing Input/Output Instructions Logical Instructions Instructions InstructionsWhen a block leaves the write buffer and returns to main memory, does anything need to happen if the processing unit makes a cache-unfulfilled request?
- 17. A file system uses an in-memory cache to cache disk blocks. The miss rate of the cache is shown in the figure. The latency to read a block from the cache is 1 ms and to read a block from the disk is 10 ms. Assume that the cost of checking whether a block exists in the7. Information can be retrieved fastest from: A) hard disk. B) magnetic tape. C) optical disk. D) USB flash drive. 8. Cache mapping is necessary because: A) the address generated by the CPU must be converted to a cache location. B) cache is so small that its use requires a map. C) cache is larger than main memory and mapping allows us to store multiple copies of each piece of data from main memory. D) None of these is correct. 9. The offset field of a main memory address is used to determine: A) if the cache entry is valid. B) if the cache entry is the desired block. C) the location of the desired data in the cache block. D) None of these is correct. 10. Cache replacement policies are necessary: A) to determine which cache mapping policy to use. B) to determine which block in cache should be the victim block. C) to decide where to put blocks when cache is empty. D) All of these are correct. 11. Cache memory is effective because: A) it is very inexpensive. B) it is very large. C) it is…Memory Management Indirect relative addressing refers to an addressing scheme in which the memory address to be accessed is specified explicitly. The memory management unit (MMU) maps virtual to physical addresses. Segmentation is a memory management approach in which memory areas (segments) allocated to processes are defined by their starting address (base) and length. The main memory is divided into two partitions when using a single-partition allocation scheme. The frame table used in systems that use paging is a per-process data structure.
- Number 2 cse .part 2 ,sir please solve this for me.it will be a great help ,you can solve it in a pageOxbe Oxe0 Oxd0 Oxb9 0xe0 Oxc5 Oxdd Ox62 0x73 Oxec Ox6c Oxc9 0x6f Ox94 Ox07 Ox08 Ox3e Oxb2 0x58 0x19 Ox89 0x5c Ox10 0OX88 oxf8 Oxf4 Ox62 0x5f Oxe6 Ox1c Ox66 0xe5 V=1;Tag=0x02; Data = v=1;Tag=0x06; Data = v=1;Tag=0x15; Data = V=0;Tag=0x1a; Data = Ox21 Oxe0 Ox05 0x31 Oxdb Ox30 0x3f 0x81 oxf9 Oxa1 Ox56 0x05 Ox84 Ox68 0xf9 0x78 Oxbd Oxa9 Ox8c Oxc2 oxba Oxe5 Oxe8 Oxac V=1;Tag=0x01; Data = v=1;Tag=0x10; Data = v=1;Tag=0x1d; Data = v=1;Tag=0x0d; Data = 10: Oxba Ox69 0x2c Ox28 Ox64 Oxe4 Ox36 Ox24 ox28 Oxb6 0x2b Ox93 Oxd9 Ox5c Oxb6 0x31 Oxbe Oxd1 Oxfe Ox23 0x13 0x37 0xbb Ox49 ox88 Ox76 Oxee 0x2f Oxao Oxa1 0x1b Ox78 V=1;Tag=0x05; Data = v=1;Tag=0x0f; Data = V=1;Tag=0x13; Data = V=0;Tag=0x1b; Data = Oxob Ox53 Ox26 0xdd Ox3d Oxe9 Ox3f 0x1f Ox02 Ox24 Ox5e Oxef Oxe1 Ox85 Ox33 Oxe3 Ox6e Oxe4 Oxb1 Ox67 Ox6e Oxfb Oxae Ox10 8: !! 9: %3D 11: V=1;Tag=0x1e; Data = v=0;Tag=0x1a; Data = v=1;Tag=0x12; Data = v=1;Tag=0x19; Data = 12: 0x19 0x21 Ox58 Oxfa оx96 Охсе Ох3с Ох23 V=1,Tag=0x1b; Data = V=1;Tag-0x18;…This function will be able to look at which fields in a log entry that it needs to. When you use 64-byte cache blocks and don't prefetch, the following code calculates the average number of cache misses for each entry in the cache.
- Paging: Select all of the following statements that are true. Systems that use paging but do not support inverted page tables maintain at least one separate page table for each process. The frame table is a system-wide data structure. When paging is applied, the selected page size determines which part of a virtual address belongs to the page number and which to the offset. The page size may differ from the frame size. The Translation Look-aside Buffer (TLB) represents a page directory for all pages in the system. Paging is prone to internal fragmentation.P2help with part A B AND C.
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