Consider a dynamically scheduled single-issue processor that uses Tomasulo's algorithm with speculation having 4 ROB entries. The latencies for ADDD and MULTD are 2 and 8 cycles respectively. Also assume that there is only1 ADDD reservation station and 1 MULTD reservation station. Fill the instruction status table for the program segment below to reflect when each instruction was issued, executed, written, and committed. Il: MULTD F1, F2, F3 12: MULTD F4, F5, F6 13: ADDD F7, F4, F5 14: ADDD F5, F8, F9 I5: ADDD F5, F7, F9

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