Suppose that you are working with a CISC machine using a 2 GHz clock (i.e., the clock ticks 2 billion times per second). This particular computer uses MASM-like instructions with the following timings: ADD reg, mem ADD reg, immed LOOP _LabelName ; 6 clock cycles ; 6 clock cycles (i.e., the ADD micro-program has 6 instructions) ; 3 clock cycles Suppose that the following code fragment is used to sum elements of a numeric array. For this problem, assume that memory limitations are non-existent and that there is no limit to the size of the array. вх, е ЕСх, МАХ_SIZE ESI, OFFSET 1ist ;initialize array pointer ;initialize sum jinitialize LOOP counter MOV MOV MOV _ProcessArray: вх, [ESI] ESI, 2 LOOP ProcessArray ;Add current list element ;Move array pointer to next element ;auto-decrement ECX, jump to more if ECX * e ADD ADD After initialization, how many array elements can be processed in 3.2 millisecond (ms)? Round your answer to the nearest integer. Note that 1 ms = 0.001 second.

Suppose that you are working with a CISC machine using a 2 GHz clock (i.e., the clock ticks 2 billion times per second). This particular computer uses MASM-like instructions with the following timings: ADD reg, mem ADD reg, immed LOOP _LabelName ; 6 clock cycles ; 6 clock cycles (i.e., the ADD micro-program has 6 instructions) ; 3 clock cycles Suppose that the following code fragment is used to sum elements of a numeric array. For this problem, assume that memory limitations are non-existent and that there is no limit to the size of the array. вх, е ЕСх, МАХ_SIZE ESI, OFFSET 1ist ;initialize array pointer ;initialize sum jinitialize LOOP counter MOV MOV MOV _ProcessArray: вх, [ESI] ESI, 2 LOOP ProcessArray ;Add current list element ;Move array pointer to next element ;auto-decrement ECX, jump to more if ECX * e ADD ADD After initialization, how many array elements can be processed in 3.2 millisecond (ms)? Round your answer to the nearest integer. Note that 1 ms = 0.001 second.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 26VE: _____ is a CPU design technique in which instruction execution is divided into multiple stages and...

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