Given an instruction sequence with instructions in classes A, B, and C as the table below (same as the last two questions): Instruction Class A BC |CPI Instruction Count|10|40|10 2 1 3 Suppose we are considering improving the execution with the following restrictions: We can only select one class of instructions to improve; and • We will be able to reduce the execution time for the selected instruction class by 50%; No changes to other instructions. Which instruction class should we select to achieve the most improvement? class A class B class C Either one: the improvement will always be the same.

Given an instruction sequence with instructions in classes A, B, and C as the table below (same as the last two questions): Instruction Class A BC |CPI Instruction Count|10|40|10 2 1 3 Suppose we are considering improving the execution with the following restrictions: We can only select one class of instructions to improve; and • We will be able to reduce the execution time for the selected instruction class by 50%; No changes to other instructions. Which instruction class should we select to achieve the most improvement? class A class B class C Either one: the improvement will always be the same.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Instructions per second is a measure of a computer's processor speed. For complex instruction set computers, different instructions take different amounts of time, so the value measured depends on the instruction. Evaluate the statement below and show how to compile it by using an instruction set machine of three-address, two-address, and one- address. A*B Y = C+D
Problem 4 There are two approaches for scheduling tasks on multiprocessor platform: the partitioned approach and the global approach. The table below shows Ci (WCET) and Ti (period) for six periodic tasks to be scheduled on m = 3 processors. The relative deadline of each periodic task is equal to its period. T T1 10 T2 10 25 T3 12 30 T4 10 T5 8. 20 T6 7 100 The task set is schedulable using rate-monotonic partitioned scheduling algorithm. Show how the task set is partitioned on m = 3 processors so that all the deadlines are met?
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Have a question requiring an answer in assembly language
i Consider two different implementations, 11 and12, of the same instruction set. There are three classes ofinstructions (A, B, and C) in the instruction set. 11 has a clockrate of 5 GHz, and 12 has a clock rate of 7 GHz. The average numberof cycles for each instruction class on 11 and 12 is given in thefollowing table: Class CPI on 11 CPI on 12 C1 Usage C2 Usage C3 Usage A 30% 25% 5% B 1 2. 40% 25% 90% 4 2 30% 50% 5% The table also contains a summary of average proportion ofinstruction classes generated by three different compilers, C1, C2,and C3. Assume that each compiler uses the same number ofinstructions for a given program but that the instruction mix is asdescribed in the table. a). Using C1, compute the average CPI for each of 1 and 12Then compute the speed, that is the average number of instructionsper second for each of 1 and 12. Then decide which one is fasterthan the other? and in what ratio? b). Using C2, compute the average CPI for each of 11 and 12Then compute the speed,…
PROBLEM 1 For sorting a set of items, we can employ one of these famous algorithms, merge- sort, heapsort, quicksort, and shell-sort. We can program in both Java and Python, and we have the choice of using three different computers with different instruction set architectures: x86, ARM, and MIPS. Regarding microarchitecture, for x86 we have two choices, and for ARM and MIPS we have three choices for each of them. How many choices we have to run a sort algorithm? (Draw diagram).
Q3: Suppose there is a processing unit composed by CPU and I/O component. For a specific task, CPU takes 5 second to finish the execution and I/O takes 2 second to process. The communication time between CPU and I/O can be elimiate under this circumstance. Execution Time 7 second 5second 2 second CPU time I/O time If CPU time decreases by 25% per year for 3 years and I/O time decreases by 20% per year 1) How many times faster is this program after 3 years? 2) What percentage of new time is I/O? and what percentage of new time is CPU?
Suppose the implementation of an instruction set architecture uses three classes of instructions, which are called A, B, and C. The total dynamic instruction count is 1 x 10^7 and the processor's clock rate is 2.5 GHz. Details for the three classes are given in the table below: Class A B C ΙΑ Complete the following table. Express all answers in scientific notation and round to two decimal places, when needed. Class Instruction Count B CPI 1 2 3 C % of instructions 20% 50% 30% x 10^ x 10^ x 10^ Number of Clock Cycles x 10^ x 10^ x 10^
1. Consider a machine running a program with four classes of instructions: A/B/C/D. The program requires 360 seconds, with the number of seconds executing each class as shown in the table below: Instruction Class A B C Time (sec) 100 80 120 60 1.1. By how much is the total execution time changed if the time for class D is reduced by 20% and the time for class C is increased by 10% (assuming no other changes)? 1.2. If we want to reduce the total execution time by 20% by optimizing class A only, what is the target execution time of class A instructions in order to achieve the reduction (assuming all other instructions are not changed)? 1.3. Can the total time be reduced by 25% if we only optimize class B? Use calculation to justify your answer.
E In the following code block(Reference:Q11), you will a set of assembly instructions with corresponding line numbers (line numbers are for informational purpose only and they are not part of the source code). 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 mov edx, 5 dec ecx jmp LABEL1 mov eax, 1 LABEL1: mul edx jmp ecx mov edx, 0678h sub edx, eax jmp DWORD PTR [edx] neg ebx add ecx, ebx mov eax, 0 For each of the conditions/scenario listed below, indicate the corresponding line number (that cause or is associated with the condition/scenario). Enter 0 (Zero) if the condition is not caused by the block of code. 1) Memory indirect jump: type your answer... type your answer... type your answer... type your answer... 2) Register indirect jump: 3) Relative short jump: type your answer... 5) Two's complement type your answer... 4) Relative near jump: 6) Unreachable code
Let (BX)=100H, DI=200H, DS 1200H, SI= F002H, AX= 0105H, and the following memory content. what is the content of SI after executing the MOV SI, [DI+BX+7H] ?instructions Memory Memory address content 12300 11 12301 AA 12302 EF 12303 80 12304 47 12305 8D 12306 5A 12307 92 12308 C5 SI = C592H O SI-F002H O SI = 92C5HO SI = EF80HO SI = 80EFHO If BL=XXH and make CMP BL,BL the sign and zero flags will be SF=1, ZF=0 O depend on the value on the BL register O SF=0, ZF=1 O SF=ZF=0 O SF=ZF=1 O