A certain processor has a physical address of 36 bits (a byte addressable memory) and a single word consists of 4 bytes = 32 bits. The cache unit is of size 256 Kbytes with line (block) size of 4 words (16 bytes). This cache has a 2-way set associative organization. The processor makes on the average, one instruction fetch and 0.45 data read/write from memory per instruction. For a block size of 4 words the measured miss rate is 1.5%. We want to investigate the possible benefits of increasing the block size to 8 words (32 Bytes). The estimated miss rate (based on simulation) for this larger block size is 1%. The cache miss penalty is equal to (6 cycles + # of words per block). Assuming that the cost of a reference that hits the cache is 1 cycle, what is the average memory access time for the two block sizes and which block size is the better choice based on the AMAT: 4 or 8 (words)? Round your answers to two decimal places. Assume that the given miss rate is same for both instruction and data.
A certain processor has a physical address of 36 bits (a byte addressable memory) and a single word consists of 4 bytes = 32 bits. The cache unit is of size 256 Kbytes with line (block) size of 4 words (16 bytes). This cache has a 2-way set associative organization. The processor makes on the average, one instruction fetch and 0.45 data read/write from memory per instruction. For a block size of 4 words the measured miss rate is 1.5%. We want to investigate the possible benefits of increasing the block size to 8 words (32 Bytes). The estimated miss rate (based on simulation) for this larger block size is 1%. The cache miss penalty is equal to (6 cycles + # of words per block). Assuming that the cost of a reference that hits the cache is 1 cycle, what is the average memory access time for the two block sizes and which block size is the better choice based on the AMAT: 4 or 8 (words)? Round your answers to two decimal places.
Assume that the given miss rate is same for both instruction and data.
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