A cache has a hit time Tc = 2 cycles and a miss rate Pmiss = 0.04. The main memory access time is Tmm = 36 cycles. The data-cache and instruction-cache have identicalperformance. A program has the following instruction distribution: probability of 0.3 for R-type instructions, 0.2 for load, 0.1 for store, and others for control instructions.Assume control instructions do not cause any loss. The processor is running at 1 GHz.Evaluate the average access time in nano-seconds of the memory system.

Given, A cache hit time tc=2 cycles miss rate=0.04 main memory access time=36 cycle . Program has R…

Answered: A cache has a hit time Tc = 2 cycles…

Computer Networking: A Top-Down Approach (7th Edition)

7th Edition

ISBN:9780133594140

Author:James Kurose, Keith Ross

Publisher:James Kurose, Keith Ross

Chapter1: Computer Networks And The Internet

Section: Chapter Questions

Problem R1RQ: What is the difference between a host and an end system? List several different types of end...

See similar textbooks

Similar questions

On the Motorola 68020 microprocessor, a cache access takes two clock cycles. Data access from main memory over the bus to the processor takes three clock cycles in the case of no wait state insertion; the data are delivered to the processor in parallel with delivery to the cache. a. Calculate the effective length of a memory cycle given a hit ratio of 0.9 and a clocking rate of 16.67 MHz. b. Repeat the calculations assuming insertion of two wait states of one cycle each per memory cycle. What conclusion can you draw from the results?
A microprocessor has an increment memory direct instruction, which adds 1 to the value in a memory location. The instruction has five stages: fetch opcode(four bus clock cycles),fetch operand address (three cycles), fetch operand (three cycles) add 1 to operand (three cycles), and store operand (three cycles). a. By what amount (in percent) will the duration of the instruction increase if we have to insert two bus wait states in each memory read and memory write operation? b. repeat assuming that the increment operation takes 13 cycles instead of 3 cycles
On the Motorola 68020 microprocessor, a cache access takes two clock cycles. Data access from main memory over the bus to the processor takes three clock cycles in the case of no wait state insertion; the data are delivered to the processor in parallel with delivery to the cache. a. Calculate the effective length of a memory cycle given a hit ratio of 0.9 and a clocking rate of 16.67 MHz. b. Repeat the calculations assuming insertion of two wait states of one cycle each per memory cycle. What conclusion can you draw from the results?
The following sequence of instructions will execute on the 5-stage pipelined MIPS datapath: I-MEM Address Instruction OXAO L1: slt $t4, $t0, $t1 OXA4 beq $t4, $1, L2 OXA8 slt $14, $t0, $t2 OXAC beq $t4, $1, L2 OXBO slt $t4, $t0, $t3 ОхВ4 beq $t4, $1, L2 OXB8 j L3 OXBC L2: addi $t0, $t0, 5 OXCO j L1 ОХC4 L3: List data dependencies for the entire code (i.e. a->b would mean instruction b is dependent on instruction a ): Which data dependencies are hazards? How many clock cycles does it take to execute the entire code for a normal pipelined processor? (i.e. all 5 stages of the last instruction have been completed) How many clock cycles will it take for a 2-issue in-order superscalar pipelined processor to execute the entire code?
Assume miss rate of an instruction cache is 2% and miss rate of data cache IS 4%, If a processor have CPI of 2 without any memory stalls and miss penalty is 100 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed. Assume frequency of all loads and stores is 36%.

Recommended textbooks for you

Computer Networking: A Top-Down Approach (7th Edi…

Computer Engineering

ISBN:

9780133594140

Author:

James Kurose, Keith Ross

Publisher:

PEARSON

Computer Organization and Design MIPS Edition, Fi…

Computer Engineering

ISBN:

9780124077263

Author:

David A. Patterson, John L. Hennessy

Publisher:

Elsevier Science

Network+ Guide to Networks (MindTap Course List)

Computer Engineering

ISBN:

9781337569330

Author:

Jill West, Tamara Dean, Jean Andrews

Publisher:

Cengage Learning

Computer Networking: A Top-Down Approach (7th Edi…

Computer Engineering

ISBN:

9780133594140

Author:

James Kurose, Keith Ross

Publisher:

PEARSON

Computer Organization and Design MIPS Edition, Fi…

Computer Engineering

ISBN:

9780124077263

Author:

David A. Patterson, John L. Hennessy

Publisher:

Elsevier Science

Network+ Guide to Networks (MindTap Course List)

Computer Engineering

ISBN:

9781337569330

Author:

Jill West, Tamara Dean, Jean Andrews

Publisher:

Cengage Learning

Concepts of Database Management

Computer Engineering

ISBN:

9781337093422

Author:

Joy L. Starks, Philip J. Pratt, Mary Z. Last

Publisher:

Cengage Learning

Prelude to Programming

Computer Engineering

ISBN:

9780133750423

Author:

VENIT, Stewart

Publisher:

Pearson Education

Sc Business Data Communications and Networking, T…

Computer Engineering

ISBN:

9781119368830

Author:

FITZGERALD

Publisher:

WILEY

SEE MORE TEXTBOOKS