7. Arsenic was pre-deposited by arsine gas, and the resulting total amount of dopant per unit area was 1×10¹4 atoms/cm². How long would it take to drive the arsenic into a junction depth of 1 µm? Assume a background doping of CB = 1×10¹5 atoms/cm³ and a drive-in temperature of 1200°C. For As diffusion, Do = 24 cm²/s, and Ea=4.08 eV. Assume 100 key boron implants on a 200 mm silicon wafer at a dose of 5x1014 ions/cm². The proiected range 8
7. Arsenic was pre-deposited by arsine gas, and the resulting total amount of dopant per unit area was 1×10¹4 atoms/cm². How long would it take to drive the arsenic into a junction depth of 1 µm? Assume a background doping of CB = 1×10¹5 atoms/cm³ and a drive-in temperature of 1200°C. For As diffusion, Do = 24 cm²/s, and Ea=4.08 eV. Assume 100 key boron implants on a 200 mm silicon wafer at a dose of 5x1014 ions/cm². The proiected range 8
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
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Transcribed Image Text:7. Arsenic was pre-deposited by arsine gas, and the resulting total amount of dopant per unit area was 1×10¹4
atoms/cm². How long would it take to drive the arsenic into a junction depth of 1 µm? Assume a background
doping of CB = 1×10¹5 atoms/cm³ and a drive-in temperature of 1200°C. For As diffusion, Do = 24 cm²/s, and
Ea = 4.08 eV.
8. Assume 100 keV boron implants on a 200 mm silicon wafer at a dose of 5×10¹4 ions/cm². The projected range
and projected straggle (op) are 0.31 and 0.07 μm, respectively. Calculate the peak concentration and the required
ion-beam current for 1 min of implantation.

Transcribed Image Text:6. Sketch a 3-input XOR and a 4-to-1 MUX by applying Transmission Gate and Pass-transistor. Compute
the number of transistors required to design those gates. Design and simulate it using the Cadence.
7. Select and analyze a latch that will mitigate all the drawbacks of a transmission gate latch. Distinguish
all the delay elements of a flip-flop.
8.
A 3-input NAND gate is designed using dynamic logic. Compute the output voltage (Vout) for this
circuit when the inputs are 1, 0, 1 (i.e., NMOS2 is receiving 0 input). Design it using the Cadence.
Simulate for different input patterns.
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