ECE526-HW#2-solutions

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California State University, Northridge *

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526

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Mechanical Engineering

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Dec 6, 2023

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ECE-526 Homework #2 California State University, Northridge 1. Write a Verilog code to design a clock with period = 200ns and a duty cycle of 25% by using always and initial statements. The value of clock at time = 0 should be initialized to 0. module clock_machine; parameter period=200, duty_cycle=25; high_time = duty_cycle*period/100; low_time = period – high_time; reg clock; always begin clock = 0; #low_time clock = 1; #high_time clock = 0; end endmodule 2. Code a Verilog module that will implement a 3 to 8 decoder with active low outputs. Any 3 to 8 decoder should be fine (behavioral , Data flow) module decoder_3to8 (out, in, en); input en; input [2:0] in; output [7:0] out; reg [7:0] out; always @(en, in) begin if (!en) begin out = 8'b0; case (in) 3'b000: out = 8'b111_11110; 3'b001: out = 8'b111_11101; 3'b010: out = 8'b111_11011; 3'b011: out = 8'b111_10111; 3'b100: out = 8'b111_01111; 3'b101: out = 8'b110_11111;
3'b110: out = 8'b101_11111; 3'b111: out = 8'b011_11111; endcase end else out = 8'b0; end endmodule 3. Use and instantiate the module that you wrote in question #2 and create a and implement a 4 to 16 decoder. module decode_4to16 (out1, en1, in1) input en1; input [3:0] in1; output [15:0] out1; reg [15:0] out1; decoder_3to8 decod1 (out [15:8], en1, in1[2:0]); decoder_3to8 decod2 (out [7:0], ~en1, in1[2:0]); endmodule 4. What will be the output after running the following initial blocks? //Initial block A initial begin x = 1; $display ("Hello, x=%d, t=%t", x, $time); #10; x = 2; $display ("Hello, x=%d, t=%t", x, $time); #25; x = 3; $display ("Hello, x=%d, t=%t", x, $time); #15; end // Initial block B initial begin #10;
x = 10; $display ("Hello, x=%d, t=%t", x, $time); #5; x = 20; $display ("Hello, x=%d, t=%t", x, $time); #20; x = 30; $display ("Hello, x=%d, t=%t", x, $time); #15; end Hello, x=1, t=0 Hello, x=2, t=10 Hello, x=3, t=35 Hello, x=10, t=10 Hello, x=20, t=15 Hello, x=30, t=35 5. Rewrite the following code using non-blocking assignments. initial begin a = #delay1 b; c = #delay2 d; End initial begin a<=#delay1 b; c<=#delay1+delay2 d; end 6. Replace the three initial blocks with only one initial block. initial a = #delay1 b; initial begin c = #delay2 d; e = #delay3 f; end
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initial begin k <= #delay4 g; h <= #delay 5 i; End intial begin a <= #delay1 b; c <= #delay2 d; e <= #delay2+delay3 f; k <= #delay4 g; h <= #delay 5 i; end