Question possible (graded, results hidden) Assume a pipelined processor with five pipeline stages where each stage takes one clock cycle. Further, assume that the processor has to execute the following instruction sequence ADD STO, ST1, ST3 ADDI $S1, S1, 4 LW $se, 0($S1) SUB S55, ss0, STO AND ST3, ST4, s5 SW $55, 0($S1) MULT $52, S56, ST3 SUB ST6, ST7, Ss6 How many stalls (in terms of the number of stall clock cycles) will the processor experience if it does not have any forwarding unit to reduce or eliminate pipeline stalls? (Assume that the write back step of an earlier instruction and the instruction decode step of a subsequent dependent instruction can happen in the same clock cycle). Calculate the total number of clock cycles needed to complete executing the instruction sequence.

Question possible (graded, results hidden) Assume a pipelined processor with five pipeline stages where each stage takes one clock cycle. Further, assume that the processor has to execute the following instruction sequence ADD STO, ST1, ST3 ADDI $S1, S1, 4 LW $se, 0($S1) SUB S55, ss0, STO AND ST3, ST4, s5 SW $55, 0($S1) MULT $52, S56, ST3 SUB ST6, ST7, Ss6 How many stalls (in terms of the number of stall clock cycles) will the processor experience if it does not have any forwarding unit to reduce or eliminate pipeline stalls? (Assume that the write back step of an earlier instruction and the instruction decode step of a subsequent dependent instruction can happen in the same clock cycle). Calculate the total number of clock cycles needed to complete executing the instruction sequence.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Computer Organization/Design Question (RISC-V). * If you solve the question correctly, I will make sure to provide a thumbs up for you. Thanks.
The design team for a simple, single-issue processor is choosing between two pipelined implementations. Here are some design parameters for the two possibilities: A B Clock Rate (MHz) 3500 2250 1 1 CPI for ALU instructions CPI for Control instructions CPI for Memory instructions 3.0 1.5 2.5 1.1 For a program with 20% ALU instructions, 15% control instructions and 65% memory instructions, which design will finish first? Give a quantitative CPI average for each case.
Figure Q4 shows a sequence of Intel x86 assembly language. ADD EAX, ECX ;load register EAX with the contents of ECX ¡plus the contents of EAX MOV EBX, EAX ;load EBX with the contents of EAX Explain steps of an instruction cycle to run the codes Illustrate a four-stage pipeline using a timing diagram for the instructions. Assume that each stage requires 1 clock cycle.
clock cycle at which the first of the instructions is fetched as clock cycle 1. Assume that if one instruction reads a register during the same clock cycle as another instruction is writing it, the new value will be read. Do not reorder the instructions. Instructions are fetched and executed exactly in the order given below, with the pipeline stalling if necessary.addi $s2, $s2, 1li $s6, 5add $s1, $s2, $s3move $s5, $s6lw $t1, 0($s5)
Assuming the given pipeline stages, explain (what and where) the potential pipeline hazard(s) (if any) in the following code segments. S1 - fetch instruction S2 - decode and calculate effective address S3 - fetch operand S4 - execute instruction and store results Instructions: 1.X = R1+ Y 2. Z = R2 + Y 3. Y = R1+X
6. Fill in the table below, assuming each instruction can impact the subsequent instructions. instruction destination result value source value addl %ecx,(%eax) sarl 2, %ebx leal 4(%eax, %edx,4), %esi movl %eax, %ebx movl (%eax), %edi 7. Assume these register values %ecx 3 %eax %ebx %edx %esi %edi Xebp %esp 120 20 Ox6010 ox6000 What changes after this instruction executes? What is its new value? imull %ecx 8. Assume these register values %ebx %eax 120 %ecx %edx %esi %edi %ebp %esp 20 Ox6010 ox6000 What changes after this instruction executes? What is its new value? idivl %ebx 9. Assuming %ecx is ox602C, what is the value at each of the locations that was placed in %al? a. movb o(%ecx), %al b. movb 1(%ecx), %al c. movb 2(%ecx), %al d. movb 3(%ecx), %al e. movb 4(%ecx), %al
CPI stands for clock cycles per instruction. Speedup from pipelining = (Number of pipeline stages) / (Achieved CPI ). Assume a 5-stage pipeline. Assume that CPI = 1 when there are no pipeline stalls (the ideal case). Now assume that every branch instruction causes a 3 clock cycle stall in the pipeline. Assume that for the program being executed 30% of executed instructions are branch instructions. What speedup from pipelining is achieved by this program?
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A particular (fictional) CPU has the following internal units and timings (WRand RR are write/read registers,ALU does all logic and integer operations and there is a separate floatingpoint unit FPU. Timings for each unit in picoseconds are:IR 230, RR 40, WR 50, ALU 200, MEM 260, FPU 380(assume instruction read and memory access are average time for access tocache)There are 5 basic instruction types: - here are instruction sequence for eachtype, time in picoseconds and percentage of each type in a typical set of testcodes:1. LOAD : IR+RR+ALU+MEM+WR : 780, 20%2. STORE: IR+RR+ALU+MEM : 730, 10%3. LOGIC/INTEGER: IR+RR+ALU+WR : 520, 40%4. FLOATING POINT: IR+RR+FPU+WR : 700, 10%5. BRANCH: IR+RR+ALU : 270, 20%1 cycle is 780ps = .780 nanoseconds for this machine, on the assumption thatall instructions take 1 cycle (assume all memory access is in cache). Clockfrequency is 1/.780 = 1.28 GHz (rounded to 2 decimals) for an ideal CPI=1
Identify data hazards, if any in the following instruction while processing through a pipelined processor. Show its implementation through a 4-stage pipelined porcessor having: Fetch Unit – Decode Unit – Execution Unit and Write Result Unit ADD R10, R2, R3 OR R8, R10, R9 XOR R1, R10, R11 AND R6, R1, R7 SUB R4, R1, R5
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Show how the instructions below would progress through the 5 stage in order pipeline Iw St5, 0(St4) add Sa0, St5, St5 sub Sa1, St5, $s2 - Assume full forwarding wherever possible. - There is no fast register file ! Read and Write to same same register need to occur in different clock cycles - Assume also the presence of a hazard detection unit in the ID stage as covered in lectures This is how you will map the pipeline diagram table to your answer: Each instruction in the pipeline stage will be shown by the letter for the pipeline stage followed by the clock cycle. That is, F2 means that in the 2nd clock cycle, the instruction is in the F stage. X7 means that in the 7th clock cycle, the instruction is in the X stage. Accordingly, the table representation for the first instruction (be), in the code sequence has been done for you Iw $t5, 0($t4):F1,D2,X3,M4,W5 This statement above previously had an errata in it which has since been corrected. Please be very careful in ensuring there are…