The design team for a simple, single-issue processor is choosing between two pipelined implementations. Here are some design parameters for the two possibilities: A B Clock Rate (MHz) 3500 2250 1 1 CPI for ALU instructions CPI for Control instructions CPI for Memory instructions 3.0 1.5 2.5 1.1 For a program with 20% ALU instructions, 15% control instructions and 65% memory instructions, which design will finish first? Give a quantitative CPI average for each case.

The design team for a simple, single-issue processor is choosing between two pipelined implementations. Here are some design parameters for the two possibilities: A B Clock Rate (MHz) 3500 2250 1 1 CPI for ALU instructions CPI for Control instructions CPI for Memory instructions 3.0 1.5 2.5 1.1 For a program with 20% ALU instructions, 15% control instructions and 65% memory instructions, which design will finish first? Give a quantitative CPI average for each case.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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A. The following measurements have been made using an architecture simulator for a processor design that is projected to have a clock rate of 1 GHz. What is the design's CPI? Instruction Frequency of CPI Class Occurrence R-type Load Branch 1 37% 25% 4 18% Store 20% В. vHow does this compare to using branch prediction to shave 1 cycle off the branch latency, but also increasing the number of cycles a store operation takes by 2 cycles?
The CPU design team is designing an instruction set with three classes of instructions. Parameters are given in the following table. Consider a program with 65% ALU instructions, 25% memory access instructions, and 10% control instructions. What is the average CPI for this CPU? Clock Rate 4GHz CPI for ALU Inst. 6 CPI for Memory Inst. 8 CPI for Control Inst. 2
9. Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of 4. The same processor is upgraded to a pipelined processor with five stages, but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume there are no stalls in the pipeline. What is the speed up achieved in this pipelined processor? Yanıtınızı girin
An instruction pipeline has tive stages mely. instruction fetch (IF), instruction ecode and register fetch (ID/RF), instruction ocution (EX), memory access (MEM), and ester writeback (WB) with stage latencies I s 22 ns, 2 ns, I ns, and 0.75 ns, espectively (ns stands for nanoseconds). To pin in terms of frequency, the designers have decided to split the ID RF stage into three
Q. What is the precise value of Ao and BHE for the instruction: MOV [19h],245k Ap — 0 and BHЕ-1 Ao 1 and BHE =0 %3| %3D Ao = 0 and BHE = 0 %3D %3| Ao =1 and BHE=1 %3D None of the other options Q. What is the precise value of Ao and BHEfor the instruction: MOV [36h] , 45? An = 0 and BHE = 1 Ap 1 and BHE = 0 Ao O and BHE = 0 Ap 1 and BHE -1 None of the other options
AziTech is considering the design of a new CPU for its new model of computer systems for 2021. It is considering choosing between two (2) CPU (CPUA and CPUB) implementationsbased on their performance. Both CPU are expected to have the same instruction set architecture. CPUA has a clock cycle time of 60 ns and CPUB has a clock cycle time of 75 ns. The same number of a particular instruction type is expected to be executed on both CPUsin order to determine which CPU would executes more instructions. CPUA is able to execute2MB of instructions in 5*106 clock cycles. CPUB executes the same number of instructions in 3*106 clock cycles.a) Using the MIPS performance metric, which of the two (2) CPU should be selected to be implemented in the new computer system. Justify your choice. b) Compute the execution time for both CPUs. Which CPU is faster?
Two different compilers are being tested for a 200 MHz’s machine with three different classes of instructions:Class A, Class B, and Class C, which require two, three and four cycles (respectively). Both compilers are used to produce code for a large piece of software. The first compiler's code uses (i+5) million Class A instructions, (i+1) million Class B instructions, and (i+1) million Class C instructions. The second compiler's code uses (i+10) million Class A instructions, (1+i) million Class B instructions, and (1+i) million Class C instructions. Where i = 24i) Which sequence has the higher MIPS rate?ii) Which sequence will be faster according to execution time
Question Q: For a basic computer that is currently running in its timing TO of execution for an instruction that is located in memory location 366. The content of AC is (212) and the content of memory locations are as follow: [memory location: content]: [365:9473], [366:7010], [367:5431], [368:4620], [431:1A23], [620:C80D]. Answer the following questions that examine the contents of PC, AR, AC, DR and IR after the end of execution for the next instruction. (Note: all numbers are in Hexadecimal.) p 4:33 The content of AC after the end of * :execution for the next instruction is 700 O 620 320 O None of the choices O 4:35 /
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2. An implementation of the above RISC-V microprocessor has been designed where the supported instructions are classified as follows with regard to the number of cycles required to execute: Arithmetic & Logic: 4 cycles Memory Access: 5 cycles 3 cycles Branching: System Calls: 1 cycle What is the average CPI for this microprocessor? (includes lui, add, addi, or, ori, sub, and, (includes all loads and stores) (includes blt, beq, bne) (includes ecall) andi)
Let's compare a CISC machine versus a RISC machine on a standard program. Assume the following characteristics of the two machines. CISC: CPI of 6 for load/store, 3 for ALU and 7 for branch, CPU clock rate of 3.5 GHz RISC: CPI of 1.2 and a CPU clock rate of 1.75 GHz Since the CISC machine has more complex instructions, the Instruction Count (1) for the CISC machine is 25% smaller than the Instruction Count (I) for the RISC machine The standard program has a breakdown of 38% loads, 10% stores, 35% ALU operations, and 17% branches. Which machine will run the standard program in less time and by how much?
4. A benchmark program is run on an 80 MHz processor. Based on the recorded measurements shown below, determine the effective CPI, MIPS rate, and execution time for this program. Instruction Type Instruction Count CPI Integer Arithmetic 30,000 1 Data Transfer 45,000 2 Floating Point 15,000 2 Control Transfer 10,000 2 Show your work for credit. Effective CPI: MIPS rate: Execution time