How can I compute sum of each of the component latencies for each instruction?Question 1:This is a three-part question about critical path calculation. Consider a simple single-cycle implementation of LEGv8 ISA. The operation times for the major functional components for this machine are as follows:Component LatencyALU90 psAdd70 psALU Control Unit30 psShifter20 psControl Unit/ROM50 psSign/zero extender20 ps2-1 MUX20 psMemory (read/write) (instruction or data)140 psPC Register (read action)20 psPC Register (write action)20 psRegister file (read action)80 psRegister file (write action)60 psLogic (1 or more levels of gates)10 ps Below is a copy of the LEGv8 single-cycle data path design. In this implementation the clock cycle is determined by the longest possible path in the machine. The critical paths for the different instruction types that need to be considered are: R-format, Load-word, and store-word. (Question 1 Part B)Place the latencies of the components that you have decided for the critical path of each instruction in the table below.Compute the sum of each of the component latencies for each instruction.Hardware Elements Time (ps)InstructionTypeR-FormatD-FormatLoadD-FormatStoreI-FormatB-FormatCB-Format Below is a copy of the LEGV8 single-cycle data path design. In this implementation the clock cycle is determined by thelongest possible path in the machine. The critical paths for the different instruction types that need to be considered are:R-format, Load-word, and store-word.PCReadaddressAddInstructionmemoryInstruction[31-0]Instruction [31-26]Instruction [25-21]Instruction [20-16]Instruction [15-11]Instruction [15-0]Control1RegDstBranchMemReadMemtoRegALU OpMemWriteALU SrcRegWriteReadregister 1Readregister 2WriteregisterWritedataRegisters Readdata 216Readdata 1Instruction [5-0]Signextend32Shiftleft 2OMUX-ALUcontrolAddALUresultZero>ALU ALUresult1AddressWritedataPCSrcReaddataDatamemoryOXER

Here is solution of Question 1 Part A.Please find in below steps.

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How can I compute sum of each of the component latencies for each instruction?

Question 1:

This is a three-part question about critical path calculation. Consider a simple single-cycle implementation of LEGv8 ISA. The operation times for the major functional components for this machine are as follows:

Component Latency

ALU	90 ps
Add	70 ps
ALU Control Unit	30 ps
Shifter	20 ps
Control Unit/ROM	50 ps
Sign/zero extender	20 ps
2-1 MUX	20 ps
Memory (read/write) (instruction or data)	140 ps
PC Register (read action)	20 ps
PC Register (write action)	20 ps
Register file (read action)	80 ps
Register file (write action)	60 ps
Logic (1 or more levels of gates)	10 ps

Below is a copy of the LEGv8 single-cycle data path design. In this implementation the clock cycle is determined by the longest possible path in the machine. The critical paths for the different instruction types that need to be considered are: R-format, Load-word, and store-word.

(Question 1 Part B)
Place the latencies of the components that you have decided for the critical path of each instruction in the table below.
Compute the sum of each of the component latencies for each instruction.
Hardware Elements Time (ps)
Instruction
Type
R-Format
D-Format
Load
D-Format
Store
I-Format
B-Format
CB-Format

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