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Assume that you have a CPU that utilizes 5 stages with the following latencies: 1) Fetch (IF) Decode (ID) Execute (ALU) Memory (Mem) 300 ps 400 ps 350 ps 550 ps Write Back (WB) 100 ps Assume that when pipelining each stage costs an extra 20ps for the registers between pipeline stages. a) b) c) For a non-pipelined processor, what is the latency of an instruction? What is the clock rate? For a pipelined processor (5 stages), what is the latency of an instruction? What is the clock rate? If you could split one of the pipeline stages into 2 equal halves, which one would you choose? What would be the new latency and clock rate with this change?

Assume that you have a CPU that utilizes 5 stages with the following latencies: 1) Fetch (IF) Decode (ID) Execute (ALU) Memory (Mem) 300 ps 400 ps 350 ps 550 ps Write Back (WB) 100 ps Assume that when pipelining each stage costs an extra 20ps for the registers between pipeline stages. a) b) c) For a non-pipelined processor, what is the latency of an instruction? What is the clock rate? For a pipelined processor (5 stages), what is the latency of an instruction? What is the clock rate? If you could split one of the pipeline stages into 2 equal halves, which one would you choose? What would be the new latency and clock rate with this change?

Database System Concepts
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
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Refer to the screenshot to solve the question on MIPS pipelining:

Assume that you have a CPU that utilizes 5 stages with the following latencies: 1) Fetch (IF) Decode (ID) Execute (ALU) Memory (Mem) 300 ps 400 ps 350 ps 550 ps Write Back (WB) 100 ps Assume that when pipelining each stage costs an extra 20ps for the registers between pipeline stages. a) b) c) For a non-pipelined processor, what is the latency of an instruction? What is the clock rate? For a pipelined processor (5 stages), what is the latency of an instruction? What is the clock rate? If you could split one of the pipeline stages into 2 equal halves, which one would you choose? What would be the new latency and clock rate with this change?
Transcribed Image Text:Assume that you have a CPU that utilizes 5 stages with the following latencies: 1) Fetch (IF) Decode (ID) Execute (ALU) Memory (Mem) 300 ps 400 ps 350 ps 550 ps Write Back (WB) 100 ps Assume that when pipelining each stage costs an extra 20ps for the registers between pipeline stages. a) b) c) For a non-pipelined processor, what is the latency of an instruction? What is the clock rate? For a pipelined processor (5 stages), what is the latency of an instruction? What is the clock rate? If you could split one of the pipeline stages into 2 equal halves, which one would you choose? What would be the new latency and clock rate with this change?
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