1. What is the primary problem when dealing with branches (such as beq and bne in ARM) in pipeline designs? You need to fetch an instruction after the branch before knowing the branch outcome Calculating if the branch should be taken or not taken complicates the design of the Execute (or ALU) stage You can have a branch dependent on a value loaded from memory which delays completing the branch Branches pose no more problem than any non-branch instruction for a pipeline

1. What is the primary problem when dealing with branches (such as beq and bne in ARM) in pipeline designs? You need to fetch an instruction after the branch before knowing the branch outcome Calculating if the branch should be taken or not taken complicates the design of the Execute (or ALU) stage You can have a branch dependent on a value loaded from memory which delays completing the branch Branches pose no more problem than any non-branch instruction for a pipeline

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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How much memory is needed to store an Array than a linked list. a. Equal b. Less c. More d. None of the above
In the event that an instruction is not accepted, it will write to VA page 30. In circumstances like these, it would be more efficient to employ a TLB that is handled by software rather than one that is maintained by hardware.
In deeper pipelines a branch prediction is very important because many more instructions are in flight and a wrong prediction would waste more time and power than that in a shallower pipeline. Select the best answer. True False
Assume the initial value for X1 is is 11 and X2 is 22. Suppose we execute the code below on a version of the pipeline from your textbook that does not handle data hazards (i.e., the programmer handles data hazards by inserting NOP instructions where necessary). What would the final values of register X5 be? Assume the register file is written at the beginning of the cycle and read at the end of a cycle. Therefore, an ID stage will return the results of a WB state occurring during the same cycle. ADDI X1,X2,#5 ADD X3,X1,X2 ADDI X4,X1,#15 ADD X5,X1,X1
Using graphical representation to show the forwarding technique cannot completely avoid the data hazard. How many stall cycles are there when the forwarding technique is used? What is the advantage of having the source register fields in a fixed location for each instruction in instruction pipeline design?
Consider the following sequence of outcomes for a particular branch instruction: T, NT, T, NT, T, NT, T, NT…. Assume this sequence repeats indefinitely. Part A: The Easy Part What is the long-term (steady-state) accuracy of the predict-taken predictor? What about predict-not-taken? Part B: 1-bit predictor What is the long-term (steady-state) accuracy of the 1-bit predictor? If its initial state matters, explain. Part C: 2-bit predictor What is the long-term (steady-state) accuracy of the 2-bit predictor? If its initial state matters, explain. Part D: Custom Predictor Design your own predictor that uses no more than 2 bits of state to maximize prediction accuracy for this pattern. Show the state diagram, and give the long-term accuracy of your predictor. If its initial state matters, explain.