Q1. Assume your computer system consists of four levels of memory including level 1 to level 3 caches and a main memory (Figure 1), with access time 0.00001us, 0.0001us, 0.001us, 0.01us and 0.1us, respectively. Further assume that the CPU accesses these memories with access frequencies 60% (L1), 25% (L2), 10% (L3) and 5% (main memory). Calculate the average access time. Level 1 Level 2 Level3 Main CPU (L1) cache (L2) cache (L3) cache Memory

Q1. Assume your computer system consists of four levels of memory including level 1 to level 3 caches and a main memory (Figure 1), with access time 0.00001us, 0.0001us, 0.001us, 0.01us and 0.1us, respectively. Further assume that the CPU accesses these memories with access frequencies 60% (L1), 25% (L2), 10% (L3) and 5% (main memory). Calculate the average access time. Level 1 Level 2 Level3 Main CPU (L1) cache (L2) cache (L3) cache Memory

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Suppose we have a byte-addressable computer using fully associative mapping with 16-bit main memory addresses and 32 blocks of cache. Supposed also that each block contains 16 bytes. The size of the offset field is 19 bits and the size of the block field is 0.625 bytes.
8 A computer consists of a processor and an I/O device D connected to main memory M via a shared bus with a data bus width of one word. The processor can execute a maximum of 106 instructions per second. An average instruction requires five ma- chine cycles, three of which use the memory bus. A memory read or write operation uses one machine cycle. Suppose that the processor is continuously executing "background" programs that require 95% of its instruction execution rate but not any I/O instructions. Assume that one processor cycle equals one bus cycle. Now suppose the I/O device is to be used to transfer very large blocks of data between M and D. a. If programmed I/O is used and each one-word I/O transfer requires the processor to execute two instructions, estimate the maximum I/O data-transfer rate, in words per second, possible through D. b. Estimate the same rate if DMA is used.
Suppose a byte-addressable computer using set-associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes.Q.) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
Suppose a byte-addressable computer using set associative cache has 8M byes of main memory and a cache of 128 blocks, where each cache block contains 64 bytes. a) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 16-way set associative, what is the format of a memory address as seen by the cache
3. A computer has a cache memory with the following features: A. Size: 16KB with lines of 32 bytes (8 words) B. Access time: 10ns The cache memory is connected to a memory using a bus. The main memory transfers a block of 8 words in 120 ns. What is the hit ratio needed to obtain an average access time of 20 ns?
Consider a 32-bit computer using byte-addressable memory accessing different types of cache. Each cache consists of 256 blocks with one 32-bit word per block. Specify how many bits are used for the tag, index or set, and byte offset for each type of cache listed in the table below.
8 A computer consists of a processor and an I/O device D connected to main memory M via a shared bus with a data bus width of one word. The processor can execute a maximum of 106 instructions per second. An average instruction requires five ma- chine cycles, three of which use the memory bus. A memory read or write operation uses one machine cycle. Suppose that the processor is continuously executing "background" programs that require 95% of its instruction execution rate but not any I/O instructions. Assume that one processor cycle equals one bus cycle. Now suppose the I/O device is to be used to transfer very large blocks of data between M and D. a. If programmed I/O is used and each one-word I/O transfer requires the processor to execute two instructions, estimate the maximum I/O data-transfer rate, in words per second, possible through D. b. Estimate the same rate if DMA is used.
please whit justification how to get the right anwser Consider a computer system with 2 levels of caches L1 and L2. L1 Cache has l-Cache and a D-Cache. The I cache has a miss rate of 17% and the D-Cache has a miss rate of 14.6%. The miss penalty to L2 cache is 13 cycles. L2 cache miss rate is 70.9% and the miss penalty to the main memory is 177 cycles.The frequency of all data operations is 34%. Assuming a processor with no memory stalls has a CPI of 3. What is the CPI with memory stalls? Select one: O a. 33.42 O b. 27.19 Oc. 46.76 O d. None of the options O e. 6231894.43 Of. 45.51
Suppose cache has a hit rate of 0.89 and access time of 5ns, main memory has a hit rate of 0.98 and access time of 60ns, and virtual memory has an access time of 700 us (microseconds). What is the average memory access time in us?
Consider a virtual memory system with the following characteristics for accessing memory: 1 nanosecond for a read operation with a hit in cache 5 nanoseconds for a read operation with a miss in cache 2 nanoseconds for a write operation with a hit in cache 10 nanoseconds for a write operation with a miss in cache The cache hit ratio is 0.9 If a sequence of instructions were executed: 100 instruction fetch operations, 60 memory operand read operations, and 40 memory operand write operations, what would be the average memory access time (in nanoseconds) in executing the sequence of instructions:
Access time 1 nanosecond L1-Cache 32 KB 32B Main Cache K 256 KB CPU memury 8 GB LI D-Cache 32B 32 KB Access time: I nanosecond Access time: 4 ranosecond Access time: 100 nanosecond Figure 1 Figure 1 illustrates a Pentium processor memory hierarchy. The Pentium processor features two caches, L1 and L2. Both caches use a 32-byte block size. L1 is located next to the CPU, whereas L2 is located between the processor and the main memory. Similar to other types of processors, the L1 cache is really two caches. The Pentium divides the L1 cache into a cache for instructions (called the I-cache) and a cache for data (called the D-coche). Rajah 1 menunjukkan hirarki ingatan Pentium pemproses. Permproses PentiLTm mempunyai dua cache, Li dan L2. Kedua-dua coche menggunakan saiz blok 32-bait. Li terletak di sebelah CPU, manakala L2 terletak di antara pemproses dan ingatan utama. Sama seperti jenis pemproses lain, cache L1 sebenarnya terdiri dari dua cache. Pentium membahagikan cache Li kepada cache…
Computer Organization: 2) Given: A MIPS computer system with 2 GB of main memory. It has an 8K-Byte direct-mapped cache with a block size of 4words.a) How many bits wide is the address bus?b) How many lines are in the cache?c) How many bits wide is the tag field?d) Show the bit field encoding for memory addresses. 3) Given the system described in question 2) above. Draw a diagram showing address and data buses, bus widths, and busdirections. Show internal cache organization and internal main memory organization.