Consider a two-tier memory system consisting of cache (SRAM) and main memory (DRAM). The cache access time is 1 nsec and the main memory access time is 50 nsecs. (1 nsec = 1 ́ 10-9 secs).
Consider a two-tier memory system consisting of cache (SRAM) and main memory (DRAM). The cache access time is 1 nsec and the main memory access time is 50 nsecs. (1 nsec = 1 ́ 10-9 secs).
Chapter4: Processor Technology And Architecture
Section: Chapter Questions
Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...
Related questions
Question
Consider a two-tier memory system consisting of cache (SRAM) and main memory (DRAM).
The cache access time is 1 nsec and the main memory access time is 50 nsecs. (1 nsec = 1 ́
10-9 secs).
(a) What is the overall memory access time given a cache hit rate of 95%?
(b) What will the cache hit rate need to be if the overall memory access time in (a) is to be
halved?
Expert Solution
This question has been solved!
Explore an expertly crafted, step-by-step solution for a thorough understanding of key concepts.
This is a popular solution!
Trending now
This is a popular solution!
Step by step
Solved in 2 steps with 1 images
Knowledge Booster
Learn more about
Need a deep-dive on the concept behind this application? Look no further. Learn more about this topic, computer-science and related others by exploring similar questions and additional content below.Recommended textbooks for you
Systems Architecture
Computer Science
ISBN:
9781305080195
Author:
Stephen D. Burd
Publisher:
Cengage Learning
Systems Architecture
Computer Science
ISBN:
9781305080195
Author:
Stephen D. Burd
Publisher:
Cengage Learning