please whit justification how to get the right anwser Consider a computer system with 2 levels of caches L1 and L2. L1 Cache has l-Cache and a D-Cache. The I cache has a miss rate of 17% and the D-Cache has a miss rate of 14.6%. The miss penalty to L2 cache is 13 cycles. L2 cache miss rate is 70.9% and the miss penalty to the main memory is 177 cycles.The frequency of all data operations is 34%. Assuming a processor with no memory stalls has a CPI of 3. What is the CPI with memory stalls? Select one: O a. 33.42 O b. 27.19 O. 46.76 O d. None of the options O e. 6231894.43 Of. 45.51

please whit justification how to get the right anwser Consider a computer system with 2 levels of caches L1 and L2. L1 Cache has l-Cache and a D-Cache. The I cache has a miss rate of 17% and the D-Cache has a miss rate of 14.6%. The miss penalty to L2 cache is 13 cycles. L2 cache miss rate is 70.9% and the miss penalty to the main memory is 177 cycles.The frequency of all data operations is 34%. Assuming a processor with no memory stalls has a CPI of 3. What is the CPI with memory stalls? Select one: O a. 33.42 O b. 27.19 O. 46.76 O d. None of the options O e. 6231894.43 Of. 45.51

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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6. A given computer has a single cache memory (off-chip) with a 2 ns hit time and a 98% hit rate. Its main memory has 40 ns access time. What is the computer's effective access time? i. ii. If an on-chip cache with a 0.5 ns hit time and a 94% hit rate is added to it, what is the computer's new effective access time? How much of a speedup does the on-chip cache give the computer? iii.
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Assume that a system is using write-though cache. It has 70% write hits. The cache operates in look-aside mode with a read-hit ratio of 80%. The program run on the system is such that it has memory reference for read 70% of time and for write is 30%. The main memory cycle time is 100ns and the cache access is 20ns.(Further assume we are using no write allocate policy) Difference between average write access time and average read access time is (in ns).
Accesses between memory tiers may be made more quickly with the use of buffers. For the given architecture, please list any buffers that may exist between the L1 and L2 caches, and between the L2 cache and the RAM.
CONSIDERIn Ocaml:type ('q, 's) transi = 'q * 's option * 'q type ('q, 's) nfa_y = { sigma : 's list; qs : 'q list; q0 : 'q; fs : 'q list; delta : ('q, 's) transi list; } So: let nfa = { sigma = ['z']; qs = [1; 2; 3]; q0 = 1; fs = [3]; delta = [(1, Some 'z', 2); (2, None, 3)] } mo n ql t, of Type: ('q, 's) nfa_y -> 'q list -> 's option -> 'q list, takes an NFA n, a set of initial states ql, and a symbol option t. It returns a set of states that the NFA might be in after starting from any state in ql and making one transition on the symbol t. So: mo nfa [1] (Some 'z') = [2]mo nfa [2] (Some 'z') = [] mo nfa [3] (Some 'z') = [] mo nfa [1;2] (Some 'z') = [2] mo nfa [2] None = [3] e_clo n ql, of Type: ('q, 's) nfa_y -> 'q list -> 'q list, takes an NFA n and a set of initial states ql. It returns a set of states that the NFA might be in after making zero or more epsilon transitions from any state in ql. So: e_clo nfa [1] = [1]e_clo nfa [2] = [2;3]e_clo nfa [3] = [3]e_clo…
A cache is organized as a 4 way set associative cache Each set's cache line consists of 4 words (meaning there are 16 bytes per line, for each set of the cache). Each set individually has one Valid bit, and one Dirty bit, for each line. The tag field of this cache is 8 bits wide. The address is 32 bits wide. Question 1a) What is the number of cache lines? Question 1b) What is the total number of 'memory bitcells' that are needed to design this cache (note, this includes the bitcells required for the tags, valid and dirty bits).
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