(i) to calculate the Cache Entry (2) (ii) as the Cache Tag (2)
Consider an ARM CPU that uses 32-bit addresses and is designed with a
direct-mapped cache. The cache is designed with 16 entries and a cache line
size of 256-bits. Assuming that the least-significant bit of the address is in bit
0, which bits of the address would be used:
(i) to calculate the Cache Entry (2)
(ii) as the Cache Tag (2)
The ARM CPU described above is used to execute the following piece of ARM
code, loaded into main memory at the addresses shown (in hexadecimal) on
the left:
...
0x00000070 SUB R5,R2,R4
0x00000074 ADD R5,R5,R7
0x00000078 MOV R9,#2
0x0000007C MUL R9,R9,R1
0x00000080 MUL R9,R9,R3
0x00000084 MOV R9,R9 ASR #8
0x00000088 ADD R3,R9,R8
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