Consider the hypothetical processor which has 256 words memory. A 19 bits instruction is placed in 1 memory cell. It supports 2-address, 1-address and 0-address instructions. It uses expanding opcode technique. If there exist five 2-address instructions and 760 1-address instructions, then number of 0-address instructions are

Consider the hypothetical processor which has 256 words memory. A 19 bits instruction is placed in 1 memory cell. It supports 2-address, 1-address and 0-address instructions. It uses expanding opcode technique. If there exist five 2-address instructions and 760 1-address instructions, then number of 0-address instructions are

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

Consider a word-addressable computer with 32 bits per word. The instruction set consists of 30 different instructions. All instructions have an operation code field, a mode field to specify one of 7 possible addressing modes, a register address field to specify one of 60 available registers, and a memory address field. Each instruction is stored in one word of memory. What is the maximum allowable size for memory? Use KB, MB, or GB as a unit.Instruction size = 32bit , allow instruction = 30 add bit = 5 Registere = 60 add bit = 8Modes = 7 add bit = 3Then: 5+8+3+address field = 32 so address filed = 16bitsNow maximum allowable size for memory = 2 ^16 * 4 bytes = 256bKB
Registers in RISC-V are 64-bit. For the sake of simplicity, consider the following instructions operating on 32-bit registers. Assume that registers x5 and x6 hold the values 0xBBBBBBBB and 0x00000000, respectively. What is the value in x6 for the followingslli x6, x5, 6 Using the result from the part above, what is the value in x6 for the following instruction. srli x6, x6, 6
A computer is having instruction length of 32 bits and operand field is 12-bits. The numbers of two-address instructions are 220 and remaining are the on e-address instructions. How many one-address instructions are 220 and remaining are the one-address instructions. How many one-address instructions are possible in this format?
Suppose that you have a computer with a memory unit of 24 bits per word. In this computer, the assembly program's instruction set consists of 198 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. a. How many bits are needed for the opcode? b. How many bits are left for the address part of the instruction? c. How many additional instructions could be added to this instruction set without exceeding the assigned number of bits? Discuss and show your calculations.
Consider the instruction ADD R1, M (R1 = R1 + [M]). M is the memory address of the operand. It is a two-word instruction – first word is the op-code and the second word is the address of the operand. Give the RTL description for the complete execution (including fetch phase) of the instruction.
Let us assume we have a CPU which supports both 3-address and 2-address instruction. The length of the instruction is 20 bits. The processor contains 64 registers. With proper reasoning and steps explain: 1. If we take minimum number of 3-address instructions, then how many maximum 2-address instruction is supported by the processor? 2. If we take maximum number of 3-address instructions, then how many minimum 2-address instruction is supported by the processor?
Compare 0-, 1-, 2-, and 3-address machines by writing programs to computeX = (A x B + C) / (D − E × B)for each of the four machines. The instructions available for use are as follows: M is a 16-bit memory address, and X, Y, and Z are either 16-bit addresses or 4-bit registers. The0-address machine uses a stack, the 1-address machine uses an accumulator, and the other two have16 registers and instructions operating on all combinations of memory locations and registers. SUB X,Y subtracts Y from X and SUB X, Y, Z subtracts Z from Y and puts the result in X. With 8-bit opcodesand instruction lengths that are multiples of 4 bits, how many bits does each machine need to computeX?
I want all steps for Consider a computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of “6” addressing modes, and it has “7” computer registers. The computer supports instructions, where each instruction consists of following fields: • Mode • Operation code • Register • Register • Memory Address Given that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction
Consider a computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of “8” addressing modes, and it has “50” computer registers. The computer supports instructions, where each instruction consists of following fields: Mode Operation code Register Register Memory Address Given that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction
In this classification, each instruction is executed uşing its own input data, independently of how other instructions get their data. We are using a(n): A Multiple Instruction Multiple Data. B Multiple Instruction Multiple Data. C Single Instruction Single Data. D Single Instruction Multiple Data
Q.1. A computer uses a memory unit with 1024 K words of 32 bits each (as shown in the figure below). A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code, a register code part to specify one of 64 registers, and an address part (15). How many bits are there in the operation code, the register code part, and the address part? Draw the instruction word format and indicate the number of bits in each part? How many bits are there in the data and address inputs of the memory?
Consider a 32-bit processor which supports 70 instructions. Each instruction is 32 bit long and has 4 fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is 8191. How many registers the processor has ?