Consider a hypothetical machine with the following characteristics: a. instruction format : (total of 12 bits, LSB is bit 0, MSB is bit 11) Opcode (4 bits) Address ( 8 bits) b. internal CPU registers: PC (Program Counter) – holds the address of the instruction IR (Instruction register) – holds the instruction to be executed A- temporary storage (8 bits) B- temporary storage (8 þits) c. partial list of opcodes M- memory address 0000 – STA M- store A to memory M 0001 – LDA M– load A from memory M 0011– STB M – store B to memory M 0101 – LDB M - load B from memory M 1000 – ADDA M– add data in M to A 1010 – ADDAB – add B to A Questions: 1. What is the maximum directly addressable memory locations? llanswer should be in decimal 2. What is the address range? l/format of answer : XXXX-XXXX where X is a hex digit 3. What is the size of PC? (express answer in terms of bits) 4. What is the size of IR? (express answer in terms of nibbles) 5. What is the maximum number of instructions?

Consider a hypothetical machine with the following characteristics: a. instruction format : (total of 12 bits, LSB is bit 0, MSB is bit 11) Opcode (4 bits) Address ( 8 bits) b. internal CPU registers: PC (Program Counter) – holds the address of the instruction IR (Instruction register) – holds the instruction to be executed A- temporary storage (8 bits) B- temporary storage (8 þits) c. partial list of opcodes M- memory address 0000 – STA M- store A to memory M 0001 – LDA M– load A from memory M 0011– STB M – store B to memory M 0101 – LDB M - load B from memory M 1000 – ADDA M– add data in M to A 1010 – ADDAB – add B to A Questions: 1. What is the maximum directly addressable memory locations? llanswer should be in decimal 2. What is the address range? l/format of answer : XXXX-XXXX where X is a hex digit 3. What is the size of PC? (express answer in terms of bits) 4. What is the size of IR? (express answer in terms of nibbles) 5. What is the maximum number of instructions?

Name: Question 5Consider a hypothetical machine with the following characte
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Description: Question 5Consider a hypothetical machine with the following characteristics:a. instruction format : (total of 12 bits, LSB is bit 0, MSB is bit 11)Opcode (4 bits)Address ( 8 bits)b. internal CPU registers:PC (Program Counter) – holds the address of

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Suppose that you have a computer with a memory unit of 24 bits per word. In this computer, the assembly program's instruction set consists of 198 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. a. How many bits are needed for the opcode? b. How many bits are left for the address part of the instruction? c. How many additional instructions could be added to this instruction set without exceeding the assigned number of bits? Discuss and show your calculations.
Q2. For the following assume that values A, B, C, D, E, and F reside in memory. Also assume that instruction operation codes are represented in 6 bits, memory addresses are 64 bits, data size is 32 bits and register addresses are 5 bits. a. For each instruction set architecture shown in Figure A.1, how many addresses or names (including both memory and register), appear in each instruction for the code to compute C = A+ B, and what is the total code size? passor TOS Memory (A) Accumulator (C) Registry (D) Re loed oore Figure A.1 Operand locations for four instruction set architecture classes. The arrows indicate whether the oper and is an input or the result of the orithmetic-logical unit ALU operation, or both an input and result Lighter shoes indicate inputs, and the dark shode indicates the result in a top of stack (TOS) register points to the top input operand, which is combined with the operand below. The first operand is removed from the stack, the result takes the place of the…
3. Suppose M8=x and M9=y. After each instruction has been executed, what is the content of the location indicated in column 3? Fill the contents in the table. Address M1 Content MMR M8 R1 MMR M9 R2 Locations Register 1 Register 2 Accumulator M7 Content М2 M3 ADD R1 R2 М4 МАМ M7 M5 HLT M7
Add Add Sum 1 Shift left 1 Branch MemRead Instruction [6-0] MemtoReg ALUOP Control MemWrite ALUSCC RegWrite L3 Instruction [19-15] Read address Read register 1 PC Instruction (24-20] Read data 1 Instruction [31-0] Read register 2 Zero ALU ALU Read Instruction [11-7) Read data 2 Address Write result data Instruction register memory Write data Registers Write Data data memoryl Instruction (31-0) 32 Imm 64 ALU Gen control Instruction [30,14-12] During a particular clock cycle, consider the CPU shown in the drawing. Assume that the following initial data is present (all values are shown in decimal, DM is Data Memory): x8=72. x18=56, DM(64) =48 During the cycle in question, assume that the following instruction is executed (the first column is the instruction's address: all values are shown in decimal): 51868 Id x8.8(x18) Write below the value of the bus L1 in decimal: L1 Write below the value of the bus L2 in decimal: L2 Write below the value of the bus L3 in decimal: L3
ISA of a hypothetical CPU 1 Address Memory: Address Data - (8-bits) LOAD M 100 25 STORE M 101 90 ADD M 102 65 SUB M 103 36 MUL M 104 22 105 77 DIV M 106 89 Where: Note: all numbers are hexadecimal M-a memory address AC - accumulator Sample program: //line 1 /line 2 //line 3 //line 4 //line 5 //line 6 LOAD 100 ADD 101 STORE 106 LOAD 102 SUB 103 STORE 105 Answer the following questions based on the given information above. 1. What is the content of memory location 106 after executing line 3? 2. What is the content of memory location 105 after executing line 6? 3. Write a program segment that will multiply the content of memory location 105 with the content of AC and store the result at memory location 100. а. b. 4. For this CPU, what is the width of the program counter? (express answer in terms of bits, do not include the word "bits" in your answer)
3. For each instruction in the table, write 8 hexadecimal digits that represent the 32 bits in the destination register after the instruction is executed. Assume s0 is 0x98AB3C6A, s1 is 0x20503666. Instructions to, 50, s1 t1, so, s1 t2, so, s1 t3, 50, 51 addi t4, 50, 0x210 wwwwwww andi t5, 50, -16 add and or xor slli t6, 50, 12 srai s2, 50, 8 Dest. reg. in 8 hexadecimal digits
In this case, every instruction receives its own data, independent of how the data for other instructions is obtained. We make advantage of a: A Multiple Data/Instruction B Multiple Iterations of Data or Instruction C Singular Data Single Inst D Singe Inst Multiple
Consider a 16-bit processor in which the following appears in the main memory, starting at location 200.a. The first part of the first word (content at 200) indicates that this instruction loads a value into an accumulator; the value of 300 in location 201 may be part of the address calculator. The mode field specifies an addressing mode and, if appropriate, indicates a source register. a. Assume that when used, the source register R1, which has a value of 500. b. There is also a base register that contains the value 100, Assume that location 249 contains the value 399, location 250 contains the value 400, and so on. Determine the effective address and the operand to be loaded for the following address modes:
A digital computer has a memory unit with 24 bits per word. The instruction set consists of 150 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address, similar to Marie). Each instruction is stored in one word of memory. a) How many bits are needed for the opcode? b) How many bits are left for the address part of the instruction? c) What is the maximum allowable size for memory?
The description of three-address instructions species the components of each type of instruction, but it does not specify the representation of these instructions in a data structure. Write the three – address code for the following expressions:(i) a = b * −c + b * −C(ii) A = −B * (C + D)(iii) (4 * 7 + 1) * 2(iv) a * - (b + c)
The execution of an instructions includes the following stages : instruction fetch, instruction decode, register fetch, ALU operation, memory operation, and write back. The analysis is based on an implementation of the datapath and control unit of a 32-bit MIPS microarchitecture.
Instruction Instruction Result Fetch Execute (a) Simplified view Wait New address Wait Instruction Instruction Result Fetch Execute Discard (b) Expanded view Figure 14.9 Two-Stage Instruction Pipeline 8. Write an assembly program that asks the user to enter numbers from the keyboard into the memory after asking him/her: "how many numbers do you want to enter?" then the program displays the sum of these entered numbers.