Suppose gaming consoles PlayStation 5 and Xbox Series X use different implementations of AMD's Zen architecture. The instructions they support can be divided into four classes according to their CPI (class A, B, C, and D). PlayStation has a clock rate of 2.7 GHz and the instruction classes have CPIs of 7, 3, 4 and 6 respectively whereas Xbox has a clock rate of 3.4 GHz and the instruction classes have CPIs of 5, 3, 3 and 1 respectively. Now suppose, a program has an instruction count of 1.0 * 108 and the instructions are divided into classes as follows: 30% class A, 50% class B, 10% class C, and 10% class D. Now answer the following questions: 1. Calculate how many more clock cycles per instruction on average does the PlayStation take compared to the Xbox?

Suppose gaming consoles PlayStation 5 and Xbox Series X use different implementations of AMD's Zen architecture. The instructions they support can be divided into four classes according to their CPI (class A, B, C, and D). PlayStation has a clock rate of 2.7 GHz and the instruction classes have CPIs of 7, 3, 4 and 6 respectively whereas Xbox has a clock rate of 3.4 GHz and the instruction classes have CPIs of 5, 3, 3 and 1 respectively. Now suppose, a program has an instruction count of 1.0 * 108 and the instructions are divided into classes as follows: 30% class A, 50% class B, 10% class C, and 10% class D. Now answer the following questions: 1. Calculate how many more clock cycles per instruction on average does the PlayStation take compared to the Xbox?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

Consider two different implementations, P1 and P2, of the same instruction setarchitecture. There are four classes of instructions (A, B, C, and D).P1 has a clock rate of 1.5 GHz and CPI for each instruction class is as follows:Class CPI for this classA 1B 2C 3D 4P2 has a clock rate of 2.0 GHz and CPI for each instruction class is as follows:Class CPI for this classA 2B 2C 2D 2a. Given a program with 106 instructions divided into classes as follows: 10% classA, 20% class B, 50% class C and 20% class D, which implementation is faster?
Consider two different implementations of the same MIPS instruction set architecture. The instructions can be divided into three classes according to their CPI (R-type, I-type, J-type). P1 with a clock rate of 2.4 GHz and CPIs of 2, 3,and 4; and P2 with a clock rate of 2.8 GHz and CPIs of 3, 3, and 3. Given a program with a dynamic instruction count of 2.0E6 instructions divided into classes as follows: 25% R-type, 35% I-type, 40% J-type, which implementation is faster? What is the global CPI for each implementation? Find the clock cycles required in both cases.
One machine uses a 2 GHz clock and executes a program with 4 classes of instructions, A, B, C, D. Their respective cycles/instruction are CPIA=3, CPIB=2, CPIC=4, and CPID=2. Another machine has a faster clock of 3.2 GHz, and a different architecture, such that the same classes of instructions have CPIA=2, CPIB=2, CPIC=3, and CPID=2. Both machines execute a program where the frequency of the four classes of instructions is 30% for Class A, 20% for Class B, 10% for Class C and 40% are instructions of Class D. a. How many instructions did each of the machines execute in 10 seconds (assume no overhead)? b. If a program has 10º instructions, which machines finishes first? c. Which machine is more performant? d. Compare the MIPS of the two machines.
Consider two different implementations of the same instruction set architecture (ISA). The instructions can be divided into three classes according to their CPI (classes A, B, and C). P1 with a clock rate of 2,5 GHz and CPIS of 1, 2, and 3, and P2 with a clock rate of 3 GHz and CPIs of 2, 2, and 4. Given a program with a dyñamic instruction count of 5 x 10 instructions divided into classes as follows: 30% class A, 30% class B, and 40% class C. A. What is the global CPI for cach implementation? B. which is faster: P1 or P27 By how much? C. Find the clock cycles required in both cases. eet
Consider two different implementations of the same instruction set architecture.The instructions can be divided into four classes according to their CPI (classA, B, C, and D). P1 with a clock rate of 2.5 GHz and CPIs of 2, 3, 4, and 4, andP2 with a clock rate of 3 GHz and CPIs of 2, 2, 3, and 1. Given a program witha dynamic instruction count of 1.0E6 instructions divided into classes asfollows: 10% class A, 20% class B, 50% class C, and 20% class D, whichimplementation is faster?
Consider two different implementations of the same instruction set architecture. Th e instructions can be divided into four classes according to their CPI (class A, B, C, and D). P1 with a clock rate of 2.5 GHz and CPIs of 1, 2, 3, and 3, and P2 with a clock rate of 3 GHz and CPIs of 2, 2, 2, and 2. Given a program with a dynamic instruction count of 1.0E6 instructions divided into classes as follows: 10% class A, 20% class B, 50% class C, and 20% class D, which implementation is faster? a. What is the global CPI for each implementation? b. Find the clock cycles required in both cases.
4. Consider two different implementations of the same instruction set architecture. The instructions can be divided into four classes according to their CPI (class A, B, C, and D). P1 with a clock rate of 2.5 GHz and CPIs of 1, 2, 3, and 3, and P2 with a clock rate of 3 GHz and CPIs of 2, 2, 2, and 2. Given a program with a dynamic instruction count of 1.0E6 instructions divided into classes as follows: 10% class A, 20% class B, 50% class C, and 20% class D, which implementation is faster? What is the global CPI for each implementation
Considertwodifferentimplementationsofthesameinstruction set architecture. The instructions can be divided into four classes according to their CPI (class A, B, C, and D). P1 with a clock rate of 2.5 GHz and CPIs of 1, 2, 3, and 3, and P2 with a clock rate of 3 GHz and CPIs of 2, 2, 2, and 2. Given a program with a dynamic instruction count of 1.0E6 instructions divided into classes as follows: 10% class A, 20% class B, 50% class C, and 20% class D, which implementation is faster? a. WhatistheglobalCPIforeachimplementation?
Consider a 32-bit processor which supports 30 instructions. Each instruction is 32 bit long and has 4 fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is 8191. How many registers the processor has?
3. Consider two different implementations of the same instruction set architecture. The instructions can be divided into four classes according to their CPI (class A, B, C, and D). P1 with a clock rate of 2.5 GHz and CPIS of 1, 2, 3, and 3, and P2 with a clock rate of 3 GHz and CPIS of 2, 2, 2, and 2. Given a program with a dynamic instruction count of 1.0E6 instructions divided into classes as follows: 10% class A, 20% class B, 50% class C, and 20% class D, which implementation is faster? a. What is the global CPI for each implementation? b. Find the clock cycles required in both cases.
Q3. Consider a set of instructions that can be divided into four classes according to their Cycles per Instruction (CPI): A, B, C, and D. Let's assume P1 and P2 are two processors that implement the same instruction set architecture in different ways. P1 has a clock rate of 2.5 GHz and CPIs of 1, 2, 3, and 3 for classes A, B, C, and D, respectively. P2's clock rate is 3 GHz and CPIs of classes A, B, C, and D are 2, 2, 2, and 2, respectively. If a program with a dynamic instruction count of 105 instructions divided into classes as follows: 10% class A, 20% class B, 50% class C, and 20% class D, which will execute the program faster: P1 or P2? Show all calculations and the formulas you are using.
Question 6 Suppose you have a RISC machine with a 1.6 GHz clock (i.e., the clock ticks 1.6 billion times per second). This particular computer uses an instruction cache, a data cache, an operand fetch unit, and an operand store unit. The instruction set includes simple instructions with the following timings: set reg, immed 2 clock cycle 2 clock cycles 2 clock cycle 4 clock cycles 3 clock cycles loop label add reg, immed add reg, reg load reg, mem Assume that the following code franent is used to sum the element of a numeric array. If the initialization code has already executed (i.e. the SET instructions have already finished execution) how many array elements can be processed in 5 ms? Round your answer to the nearest integer. Recall that 1 ms = 0.001 seconds. Also assume that there are no physical memory limitations, implying that the array can be as large as desired. ri, e r2, MAX_SIZE ;initialize loop counter r3, @list initialize sum set set set initialize array pointer more: load…