Consider a two level memory hierarchy of the form (L1, L2) where L1 is connected directly to the CPU. Determine the average cost per bit and average access time for the data given below. Level L1 L2 Capacity Cost 1024 216 0.1000 0.0100 Access time Hit ratio 10-8 0.9000 106
Consider a two level memory hierarchy of the form (L1, L2) where L1 is connected directly to the CPU. Determine the average cost per bit and average access time for the data given below. Level L1 L2 Capacity Cost 1024 216 0.1000 0.0100 Access time Hit ratio 10-8 0.9000 106
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
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![6.
7.
Consider a two level memory hierarchy of the form (L1, L2) where L1 is connected directly to the CPU.
Determine the average cost per bit and average access time for the data given below.
Access time Hit ratio
10.8
0.9000
106
Level Capacity Cost
1024
0.1000
L1
216
0.0100
L2
It is necessary to transfer 512 words from a backup store to a memory section starting from address
1000 and the transfer is by means of DMA. I) What are the initial values that the CPU must transfer to
the DMA controller? Give step by step account of the actions taken during the input of the first two
DWD
words.](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F98b4df0e-1f7b-4d1a-b36f-bfd9153b38a3%2Fb504c7d6-c1df-42c8-beb8-0af065b7b35a%2Fina56oi_processed.jpeg&w=3840&q=75)
Transcribed Image Text:6.
7.
Consider a two level memory hierarchy of the form (L1, L2) where L1 is connected directly to the CPU.
Determine the average cost per bit and average access time for the data given below.
Access time Hit ratio
10.8
0.9000
106
Level Capacity Cost
1024
0.1000
L1
216
0.0100
L2
It is necessary to transfer 512 words from a backup store to a memory section starting from address
1000 and the transfer is by means of DMA. I) What are the initial values that the CPU must transfer to
the DMA controller? Give step by step account of the actions taken during the input of the first two
DWD
words.
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