a. Calculate the effective length of a memory cycle given a hit ratio of 0.9 and a clocking rate of 16.67 MHz. b. Repeat the calculations assuming insertion of two wait states of one cycle each per memory cycle. What conclusion can you draw from the results?
a. Calculate the effective length of a memory cycle given a hit ratio of 0.9 and a clocking rate of 16.67 MHz. b. Repeat the calculations assuming insertion of two wait states of one cycle each per memory cycle. What conclusion can you draw from the results?
Chapter4: Processor Technology And Architecture
Section: Chapter Questions
Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...
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![On the Motorola 68020 microprocessor, a cache access takes two
clock cycles. Data access from main memory over the bus to the
processor takes three clock cycles in the case of no wait state
insertion; the data are delivered to the processor in parallel with
delivery to the cache.
a. Calculate the effective length of a memory cycle given a hit
ratio of 0.9 and a clocking rate of 16.67 MHz.
b. Repeat the calculations assuming insertion of two wait states
of one cycle each per memory cycle. What conclusion can you
draw from the results?](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F919d2390-c247-4e4c-8837-57ac9e9b307a%2F16f1c6ef-073f-4cc6-a9b4-734f2183d097%2Fv9i5l8_processed.jpeg&w=3840&q=75)
Transcribed Image Text:On the Motorola 68020 microprocessor, a cache access takes two
clock cycles. Data access from main memory over the bus to the
processor takes three clock cycles in the case of no wait state
insertion; the data are delivered to the processor in parallel with
delivery to the cache.
a. Calculate the effective length of a memory cycle given a hit
ratio of 0.9 and a clocking rate of 16.67 MHz.
b. Repeat the calculations assuming insertion of two wait states
of one cycle each per memory cycle. What conclusion can you
draw from the results?
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