Consider a hypothetical system, a 48-bit width main memory with a capacity 256 TB is build using 64 T x 8-bit DRAM chips. The number of rows of memory cells in the DRAM is 225. The time taken to perform one Refresh operation is 40 ns. The refresh period is 5 s. Fraction of total memory bandwidth is lost to refresh cycle is (up to two decimal places).

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