Consider a cache memory with blocks of 23 = words (1 word = 4 bytes) , with a bus Main Memory - Cache of 32 bits, and with 1 clock cycle to send the address, a row cycle time (DRAM) of 17 cycles (5 less clock cycles for the column access time) and 1 clock cycle to return a word. Assuming that each word is in a different DRAM row, calculate the bandwidth of the system in byte per clock cycles (bandwidth = number of bytes per clock cycles) for the transfer of one block from Main Memory to Cache Memory (not interleaved memory system). Provide the solution with at least 2 decimals

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
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Consider a cache memory with blocks of 2= words (1 word = 4 bytes) , with a bus Main Memory - Cache of 32 bits, and with 1 clock cycle to send the address, a row cycle time (DRAM) of 17 cycles (5 less clock cycles for the column access time) and 1 clock cycle to return a word. Assuming that each word is in a different DRAM row, calculate the bandwidth of the system in byte per clock cycles (bandwidth = number of bytes per clock cycles) for the transfer of one block from Main Memory to Cache Memory (not interleaved memory system). Provide the solution with at least 2 decimals 

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