Assuming write-back caches, private L1 data caches (L1Ds) (no L2), shared memory, and a MESI coherence policy, indicate in the cache tables what would be the values (V) of the variables X and Y and their coherency (C) state (either M, E, S or I) in the L1D's for a dual core processor with the following sequence of reads and writes. As shown in the table, the coherency (C) state in Step 0 (the initial coherency state) of both variables in both caches is I (invalid). If a value doesn't change, you may leave that entry blank. You may use either the state transition diagram or the table given below to reason about cache coherence. Step 0: Step 1: Step 2: Initially, X =3, Y = 5 in the shared memory, processor caches are empty Core 1 reads X (from the shared memory) Core 2 reads X Core 1 writes X = 2 Core 1 writes Y = 6 Step 3: Step 4: Step 5: Core 2 reads Y Please fill in the following cache and shared memory tables (no further explanation for your answers is required).
Assuming write-back caches, private L1 data caches (L1Ds) (no L2), shared memory, and a MESI coherence policy, indicate in the cache tables what would be the values (V) of the variables X and Y and their coherency (C) state (either M, E, S or I) in the L1D's for a dual core processor with the following sequence of reads and writes. As shown in the table, the coherency (C) state in Step 0 (the initial coherency state) of both variables in both caches is I (invalid). If a value doesn't change, you may leave that entry blank. You may use either the state transition diagram or the table given below to reason about cache coherence. Step 0: Step 1: Step 2: Initially, X =3, Y = 5 in the shared memory, processor caches are empty Core 1 reads X (from the shared memory) Core 2 reads X Core 1 writes X = 2 Core 1 writes Y = 6 Step 3: Step 4: Step 5: Core 2 reads Y Please fill in the following cache and shared memory tables (no further explanation for your answers is required).
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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![Assuming write-back caches, private L1 data caches (L1Ds) (no L2), shared memory, and a MESI coherence
policy, indicate in the cache tables what would be the values (V) of the variables X and Y and their coherency
(C) state (either M, E, S or I) in the L1D's for a dual core processor with the following sequence of reads and
writes. As shown in the table, the coherency (C) state in Step 0 (the initial coherency state) of both variables
in both caches is I (invalid). If a value doesn't change, you may leave that entry blank. You may use either the
state transition diagram or the table given below to reason about cache coherence.
Step 0:
Step 1:
Step 2:
Step 3:
Step 4:
Initially, X =3, Y = 5 in the shared memory, processor caches are empty
Core 1 reads X (from the shared memory)
Core 2 reads X
Core 1 writes X = 2
Core 1 writes Y = 6
Step 5: Core 2 reads Y
Please fill in the following cache and shared memory tables (no further explanation for your answers is required).
Core 1's L1D Cache (private)
Step 1 Step 2
Step 3
V с
V с
V C
X
Y
X
Y
X
Y
Step 0
V C
I
I
Step 0
V C
I
I
-
Core 2's L1D Cache (private)
Step 1
Step 2 Step 3
V с
V с
V с
Step 0 Step 1
V
V
3
5
Shared memory
Step 2
V
Step 4
V с
Step 3
V
Step 4
V C
Step 4
V
Step 5
V C
Step 5
V с
Step 5
V](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Fc4e73072-742e-4396-bcf5-c77a627ec718%2Fbf2192df-0959-4564-a0d2-f9a0b86374ac%2Fkj4ft8_processed.png&w=3840&q=75)
Transcribed Image Text:Assuming write-back caches, private L1 data caches (L1Ds) (no L2), shared memory, and a MESI coherence
policy, indicate in the cache tables what would be the values (V) of the variables X and Y and their coherency
(C) state (either M, E, S or I) in the L1D's for a dual core processor with the following sequence of reads and
writes. As shown in the table, the coherency (C) state in Step 0 (the initial coherency state) of both variables
in both caches is I (invalid). If a value doesn't change, you may leave that entry blank. You may use either the
state transition diagram or the table given below to reason about cache coherence.
Step 0:
Step 1:
Step 2:
Step 3:
Step 4:
Initially, X =3, Y = 5 in the shared memory, processor caches are empty
Core 1 reads X (from the shared memory)
Core 2 reads X
Core 1 writes X = 2
Core 1 writes Y = 6
Step 5: Core 2 reads Y
Please fill in the following cache and shared memory tables (no further explanation for your answers is required).
Core 1's L1D Cache (private)
Step 1 Step 2
Step 3
V с
V с
V C
X
Y
X
Y
X
Y
Step 0
V C
I
I
Step 0
V C
I
I
-
Core 2's L1D Cache (private)
Step 1
Step 2 Step 3
V с
V с
V с
Step 0 Step 1
V
V
3
5
Shared memory
Step 2
V
Step 4
V с
Step 3
V
Step 4
V C
Step 4
V
Step 5
V C
Step 5
V с
Step 5
V
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