Develop a hypothetical architecture with illustrative instruction and data formats, instruction sets, etc., and a short program (at least, with eight data entry from keyboard, data storage to three memory locations, and the "maximum" value calculation of the data entered from the keyboard) to compare the three cache mapping algorithms. Indicate the corresponding run-time register contents and justify all architectural, etc., selections sufficiently. CAN YOU EXPLAIN WITH THE EXAMPLE USING NUMBERS IN THE STACKS FROM THE IMAGE WITH EACH STEP INSTEAD OF PROGRAM.
Develop a hypothetical architecture with illustrative instruction and data formats, instruction sets, etc., and a short
CAN YOU EXPLAIN WITH THE EXAMPLE USING NUMBERS IN THE STACKS FROM THE IMAGE WITH EACH STEP INSTEAD OF PROGRAM.
Solution ::
Op-field: specifies the operation to be performed;
Address-field: provides operands or the CPU register/MM addresses of the operands.
Example:
\begin{displaymath}X=(A+B)*(C+D) \end{displaymath}
where $A$, $B$, $C$, $D$ and $X$ are five main memory locations representing five variables;
3-address format:
Assume variables A, B, C, D, and X are stored in MM locations labeled by their names.
ADD R1 A B # R1 $\leftarrow$ [A] + [B]
ADD R2 C D # R2 $\leftarrow$ [C] + [D]
MUL X R1 R2 # X $\leftarrow$ [R1] $\times$ [R2]
Note: here we assume an instruction \fbox{OP dst src1 src2} means:
\begin{displaymath}dst \leftarrow [src1] * [src2]
\end{displaymath}
where src1 and src2 are the source operand, dst is the destination operand, and * represents the operation specified in Op-code field OP.
2-address format:
MOV R1 A # R1 $\leftarrow$ [A]
ADD R1 B # R1 $\leftarrow$ [B] + [R1]
MOV R2 C # R2 $\leftarrow$ [C]
ADD R2 D # R2 $\leftarrow$ [D] + [R2]
MUL R2 R1 # R2 $\leftarrow$ [R1] $\times$ [R2]
MOV X R2 # X $\leftarrow$ [R2]
Note: here we assume an instruction \fbox{OP dst src} means:
\begin{displaymath}dst \leftarrow [dst] * [src]
\end{displaymath}
Trending now
This is a popular solution!
Step by step
Solved in 3 steps
