(a) Suppose you could build a CPU where the clock cycle time was different for each instruction. What would the speedup of this newCPU be over the CPU presented in COD Figure 4.23 (The simple control and datapath...) given the instruction mix below?LDURSTURCBZB25%10%11%2%R-type/I-Type52% Figure 4.4.10: The simple control and datapath are extended to handle the unconditional branchinstruction (COD Figure 4.23).An additional OR-gate (at the upper right) is used to control the multiplexer that chooses between the branch target and the sequentialinstruction following this one. One input to the OR-gate is the Uncondbranch control signal. Although not shown, the Sign-extend logicwould recognize the unconditional branch opcode and sign-extend the lower 26 bits of the branch instruction to form a 64-bit address tobe added to the PC.PC4->AddReadaddressInstruction[31-0]InstructionmemoryInstruction [31-21]Instruction [9-5]Instruction [20-16]Instruction [4-0]ControlInstruction [31-0]Reg2LocUncondbranchBranchMemReadMemtoRegALUOPMemWriteALUSrcRegWritehogyReadregister 1 Readdata 1Readregister 232ReadWriteregister data 2Writedata RegistersSign-extend64Instruction [31-21]Shiftleft 2,MSXALUAdd resultZeroALU ALUresultALUcontrolAddressReaddataWrite Datadata memory

Name: (a) Suppose you could build a CPU where the clock cycle time was diff
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Description: (a) Suppose you could build a CPU where the clock cycle time was different for each instruction. What would the speedup of this newCPU be over the CPU presented in COD Figure 4.23 (The simple control and datapath...) given the instruction mix below?

Amdahl's Law can be defined in such a way that it is a fundamental concept in laptop structure and parallel computing that allows know-how of the capability speedup of a software or system when you introduce parallel processing.To answer this question, we need to calculate the common clock cycle time of the brand-new CPU. we can do that by weighting the clock cycle time of each instruction via its frequency inside the instruction blend.1Average clock cycle time = (0.25 * LDUR_cycle_time) + (0.10 * STUR_cycle_time) + (0.11 * CBZ_cycle_time) 2we are for the reason that the clock cycle time of the brand new CPU is exclusive for every education. shall we embrace that the clock cycle times are as follows:1LDUR_cycle_time = 10 ns 2STUR_cycle_time = 15 ns 3CBZ_cycle_time = 12 nsSubstituting these values into the equation above, we get the following average clock cycle time:1Average clock cycle time = (0.25 * 10 ns) + (0.10 * 15 ns) + (0.11 * 12 ns) = 11.55 nsThe clock cycle time of the CPU presented in COD Figure 4.23 is 12 ns. Therefore, the speedup of the new CPU would be:1Speedup = (12 ns) / (11.55 ns) = 1.039New CPU would be 3.9% faster than the CPU presented in COD Figure 4.23.New CPU would be 3.9% faster than the CPU presented in COD Figure 4.23.

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a) Suppose you could build a CPU where the clock cycle time was different for each instruction. What would the speedup of this ne CPU be over the CPU presented in COD Figure 4.23 (The simple control and datapath...) given the instruction mix below? R-type/I-Type LDUR STUR CBZ B 52% 25% 10% 11% 2%

a) Suppose you could build a CPU where the clock cycle time was different for each instruction. What would the speedup of this ne CPU be over the CPU presented in COD Figure 4.23 (The simple control and datapath...) given the instruction mix below? R-type/I-Type LDUR STUR CBZ B 52% 25% 10% 11% 2%

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Question

(a) Suppose you could build a CPU where the clock cycle time was different for each instruction. What would the speedup of this new
CPU be over the CPU presented in COD Figure 4.23 (The simple control and datapath...) given the instruction mix below?
LDUR
STUR
CBZ
B
25%
10%
11%
2%
R-type/I-Type
52%

Figure 4.4.10: The simple control and datapath are extended to handle the unconditional branch
instruction (COD Figure 4.23).
An additional OR-gate (at the upper right) is used to control the multiplexer that chooses between the branch target and the sequential
instruction following this one. One input to the OR-gate is the Uncondbranch control signal. Although not shown, the Sign-extend logic
would recognize the unconditional branch opcode and sign-extend the lower 26 bits of the branch instruction to form a 64-bit address to
be added to the PC.
PC
4-
>Add
Read
address
Instruction
[31-0]
Instruction
memory
Instruction [31-21]
Instruction [9-5]
Instruction [20-16]
Instruction [4-0]
Control
Instruction [31-0]
Reg2Loc
Uncondbranch
Branch
MemRead
MemtoReg
ALUOP
MemWrite
ALUSrc
RegWrite
hogy
Read
register 1 Read
data 1
Read
register 2
32
Read
Write
register data 2
Write
data Registers
Sign-
extend
64
Instruction [31-21]
Shift
left 2,
MSX
ALU
Add result
Zero
ALU ALU
result
ALU
control
Address
Read
data
Write Data
data memory

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