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3) A computer has 8 GByte of memory with 64 bit word sizes. Each block of memory stores 16 words. The computer has a direct-mapped cache of 128 blocks. The computer uses word-level addressing which means that the offset refers to individual words (not bytes) in the block. a) What is the address format? Give the total number of bits needed and how the bits are distributed between the tag, index (which block) and offset. b) If we change the cache to a 4-way set associative cache, what would be the address format?

3) A computer has 8 GByte of memory with 64 bit word sizes. Each block of memory stores 16 words. The computer has a direct-mapped cache of 128 blocks. The computer uses word-level addressing which means that the offset refers to individual words (not bytes) in the block. a) What is the address format? Give the total number of bits needed and how the bits are distributed between the tag, index (which block) and offset. b) If we change the cache to a 4-way set associative cache, what would be the address format?

Systems Architecture
Systems Architecture
7th Edition
ISBN:9781305080195
Author:Stephen D. Burd
Publisher:Stephen D. Burd
Chapter11: Operating Systems
Section: Chapter Questions
Problem 26VE
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3) A computer has 8 GByte of memory with 64 bit word sizes. Each block of memory stores 16 words. The computer has a direct-mapped cache of 128 blocks. The computer uses word-level addressing which means that the offset refers to individual words (not bytes) in the block. a) What is the address format? Give the total number of bits needed and how the bits are distributed between the tag, index (which block) and offset. b) If we change the cache to a 4-way set associative cache, what would be the address format?
Transcribed Image Text:3) A computer has 8 GByte of memory with 64 bit word sizes. Each block of memory stores 16 words. The computer has a direct-mapped cache of 128 blocks. The computer uses word-level addressing which means that the offset refers to individual words (not bytes) in the block. a) What is the address format? Give the total number of bits needed and how the bits are distributed between the tag, index (which block) and offset. b) If we change the cache to a 4-way set associative cache, what would be the address format?
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