lab2 (1)

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3701C

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Electrical Engineering

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Jan 9, 2024

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EEL 3701C – Digital Logic & Computer System LAB 2 ( 45 Pts, 10 Pts bonus, Due 10/15/2023, 11:59 PM ) NB: Most of the code for this homework are provided on the VHDL Overview slides Problem 1: Design and Implementation of a counter on the DE10-Lite FPGA Board The figure below illustrated the architecture of a counter for the following counting sequence: 0-5-2-1-4- 3-6-9-8-7-0 Figure 1 Structural Implementation of a Counter The counter consists of the following modules: - 4 instances of a D-FlipFlop to store the current number. In addition to the clock, the FlipFlops have a reset input that clear the FlipFlop by setting the output to 0. - A combinational block to compute the next counter value as function of the current counter value. The result will become the current counter value on a rising edge of the clock. - A BCD converter that takes the 4 outputs of the counter (as digital number) and produces the corresponding decimal number. The outputs of the BCD converter are directly connected to the pins of a seven-segment (SSG) display. Your BCD converter of the previous lab can be used here. Pre-Lab Homework (18 pts) 1. Provide the VHDL design of the counter circuit a) Identify the inputs outputs and input-outputs of the circuit (1 pt) b) Provide the entity declaration circuit (2 pts) c) Devise the VHDL description of the combinational. This is achieved by drawing the truth table of the next states as function of the current state (5 pts) . d) Provide the architecture description of the circuit. Define the components, the signals, instantiate all components (4 D-FF and 1B and connect the components using the internal and ports (6 pts) .

2. Put everything together, compile and correct all possible errors. Also, complete pin assignment, using the DE-10 Lite manual. Use a switch or a push button as reset input. (4 pts) In-Lab Implementation (10 pts) 1. Complete the pin assignment, and synthesize, download, and test your design on the DE-10 Lite board (10 pts) . Problem 2: Clock Divider Circuit You can notice that the seven-segment display is not changing. The clock frequency is too high for you to see anything. The SSG is probably on but not solid on, which indicates a high-speed clock. An external oscillator drives the DE-10 Lite device that we are using with a clock frequency of 10 MHz on pin PIN_N5 (see DE-10 Lite manual page 24 on Canvas). If a 10MHz clock drives the SSG on the DE-10 Lite board, the changes on the SSG will not be viewable as transitions will happen faster than the human eye can see. In the second part of this design, we want to use a much slower clock and observe the changes at the output. We will therefore use a module called clock divider (Clk_Div on figure 2) to slow down the clock. The block diagram of the resulting circuit is shown in the following figure ( Figure 2 ). Figure 2: Synchronous circuit with clock divider The VDHL code of the overall circuit is provided below in figure Figure 4 . We use a process clock divider to generate a slower clock. The clock divider is a process that takes as input the base clock and generates a slower clock.

Figure 3: Fast and slow clock The clock divider uses a binary counter to count the number of main clock pulses. Upon reaching the dividing value, the slower clock signal is generated. Figure 3 illustrates the behavior of the clock divider that slows down the base clock by 4, i.e., each slow clock occurs after four base clock cycles. In VHDL coding, two ways are followed to detect the clock signal's rising edge/falling edge. 1. if ( rising_edge ( clock )) then 2. if ( clock = '1' and clock' event ) then After detecting a rising edge/falling edge on the base clock cycle, we can start an internal counter and count till our desired clock cycles of slower clock. After finishing the counting, we enable the slower clock. For example, if we have a base clock of 4 MHz (4 million clock cycles per second) and want to generate a clock of 1 Hz (1 clock cycle per second), we must count 4 million clock cycles to achieve a one Hz clock. Remember, every clock cycle has one positive cycle (rising edge) and one negative cycle (falling edge). Thus, 4 MHz (4 million clock cycles per second) clock signal has 4 million positive and 4 million negative cycles. One easy way of counting the required number is to follow this equation: ?𝑎?𝑒 𝑐??𝑐? 𝐹?𝑒??𝑒?𝑐𝑦 2 𝑆??𝑤𝑒? ???𝑐? 𝐹?𝑒??𝑒?𝑐𝑦 If we take a 50 MHz base clock and wants to generate a 50 Hz slower clock, the counting number will be, 50 ∗ 10 6 2 50 = 500,000 𝑐????

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Figure 4: VHDL Code 1 - LED blinker using clock divider Understand the code in Figure 4 and verify that the VHDL code matches the behavior on the picture. The code has been written for 1 Hz slower clock when the base is 4MHz clock and the count for 1 Hz is 2,000,000. In the provided code, a very effective comparing of std_logic_vector were given which uses the uncount and to_unsigned function ( Figure 4 Line 29 ). Students are advised to observe the data type comparison very carefully. To exploit the effectiveness of these two functions, the provided library headers must be included in the code. Pre-Lab Homework (10 pts) 1- Calculate the value of the count if we want a 5 sec clock period if we use the 10 MHz on board clock as a base clock. (5 pts) 2- Use the VHDL code of Figure 4 to assemble your top-level entity. Compile and make sure your code is free of errors. (5 pts) In-Lab Implementation (7 pts) Synthesize your design, download, and test it on the FPGA board. (7 pts) Document your observation. Use the schematic viewer ( Tools-> Netlist Viewers->RTL Viewer ) to visualize the structure of the circuit. Bonus: Two Digit Counter (10 pts) Implement a counter for the following sequence (00 – 05 – 07 – 10 – 12 – 15 – 00) and display the output on two seven segment displays N.B All Pre-Lab HomeWorks must be completed before your lab session. You will not be admitted to the lab without completing this part.