Lab report 4-124

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San Jose State University *

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124

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Electrical Engineering

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Apr 3, 2024

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Lab 4: 4-bit Counter I. INTRODUCTION This lab involves creating a 4-bit counter in RTL Verilog, incorporating a 4-bit Ripple Carry Adder, four 2-to-1 Multiplexers, and four D-type flip-flops. The counter, with active-low reset, exhibits forward counting (0000 to 1111) when Reset is 1 and Count is 1. When Reset is 1 and Count is 0, the counter stalls, requiring observation of transitions between logic 0 and 1 for Count to validate the circuit. This exercise offers practical experience in RTL Verilog for digital circuit design, emphasizing comprehensive testing for circuit validation. II. LOGIC CIRCUIT Fig 1. Logic Circuit Diagram for 4-bit counter Figure 1 shows the logic circuit diagram for a 4-bit counter which has four 2:1 MUXes and four D-type flip flops. III. TRUTH TABLE Reset Clock Count Q3 Q2 Q1 Q0 0 X X 0 0 0 0 1 ^ X 0 0 0 1 1 ^ X 0 0 1 0 1 ^ X 0 0 1 1 1 ^ X 1 1 1 0 1 ^ X 1 1 1 1 0 X X 0 0 0 0 1 ^ 0 0 0 0 0 1 ^ 1 0 0 0 1 Fig 2. Logic Circuit Diagram for 4-Bit Counter Figure 2 is the truth table for a 4- bit counter. The prompt can be generated by listing all possible combinations of inputs (Reset, Clock, and Count) and the corresponding outputs (Q3, Q2, Q1, Q0). “X” represents don’t care case here and “^” indicates a rising edge of the clock signal. IV. CODE Fig 3. Verilog code for 4- Bit Counter (Part-1)

Fig 4. Verilog code for 4- Bit Counter (Part-2) Fig 5. Verilog code for 4- Bit Counter (Part-3) Figure 3, figure 4 and figure 5 represents the code for the 4-bit counter. This Verilog code defines a 4-bit counter with a ripple carry adder (RCA), 2-1 MUXes, and D-type flip-flops. The counter increments on each rising edge of the clock when the count input is asserted (Count = 1). It resets to zero when the active-low reset (rst_n) is low. When Count is de-asserted (Count = 0), the counter stalls, holding its current state. The code ensures the desired forward counting behavior and includes provisions for active-low reset and count control. V. SIMULATION WAVEFORMS Fig 6. 4-Bit Counter Simulation Waveforms (Part-1) Fig 7. 4-Bit Counter Simulation Waveforms (Part-2) Figure 6 and Figure 7 shows the Simulation waveform for 4-bit counter. The waveform also matches with the Truth Table and the Logic Circuit Diagram. When simulating the Verilog code, we observe a sequence of counter increments when Count is 1 and stalling when Count is 0. Resetting the counter should set it to 0000, and transitions of the Reset signal should control the reset behavior. The clock signal drives the counter updates. VI. CONCLUSION In conclusion, the provided Verilog code successfully implements a 4-bit counter using a combination of a ripple carry adder, 2-1 MUXes, and D-type flip-flops. The counter exhibits expected behavior, incrementing on clock edges when the count input is high and resetting to zero on an active-low reset signal. The code allows for thorough verification of the counter's functionality, including forward counting and the ability to stall when the count input is low. The modular structure enhances readability and facilitates customization for specific applications.

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