02Design a 2-digit decade counter that counts from 00 to 59 and repeats. Use two cascaded synchronous binarycounters (74LS163) and other basic logic gates to implement. Simulate the complete counter circuit by OrCADand PSPICE. Capture the circuit schematic and the simulated waveform.. (Define the simulation timings for atleast one full counting cycle from 0 to 59 and back to 0.)Q3Repeat Q2, modify the design to implement a 2-digit decade counter that counts from 33 to 77 and repeats. Usetwo cascaded synchronous binary counters (74LS163) and other basic logic gates to implement. Simulate thecomplete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform.(Define the simulation timings for at least one full counting cycle from 33 to 77 and back to 33.) a) Design a single-digit decade counter that counts from 0 to 9 and repeats. The single-digit decade countershould be built by a cascaded synchronous binary counter (74LS163) and other basic logic gates. Simulatethe complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulatedwaveform. (Define the simulation timings for at least one full counting cycle from 0 to 9 and back to 0.)(Hint: Use the DigClock input from the SOURCE as shown below and setup the CLK ONTIME andOFFTIME accordingly for the clock source.)1/6PatDigClockPart ListOFFTIME = SuS DSTM1ONTIME =DELAY=STARTVAL = 0OPPVAL = 1SusEUKFleStimACLbrajesDesign Cacheb) Read the specification of 74LS47 (BCD-to-7-Segment Decoder shown in Appendix) to see how the logic ICoperates to drive a 7-segment LED display. Draw the circuit connection of the decade counter in (a) and thedecoder to display the count value on the 7-segment LED display. Further explain why common anodeconfiguration is needed for our 7-segment display rather than the common cathode configuration.

According to guidelines we need to solve only the first question. According to the question we have…

Design a 2-digit decade counter that counts from 00 to 59 and repeats. Use two cascaded synchronous binary counters (74LS163) and other basic logic gates to implement. Simulate the complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform. . (Define the simulation timings for at least one full counting cycle from 0 to 59 and back to 0.)

Design a 2-digit decade counter that counts from 00 to 59 and repeats. Use two cascaded synchronous binary counters (74LS163) and other basic logic gates to implement. Simulate the complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform. . (Define the simulation timings for at least one full counting cycle from 0 to 59 and back to 0.)

Introductory Circuit Analysis (13th Edition)

13th Edition

ISBN:9780133923605

Author:Robert L. Boylestad

Publisher:Robert L. Boylestad

Chapter1: Introduction

Section: Chapter Questions

Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...

See similar textbooks

Similar questions

The need to use forward error control is to
* Include memory elements and ........ combinational circuit Sequential network Integrated circuit Programmable logic array O O
30) Coils labeled ( S ) and ( R )A) must appear in that order (S before R) in a ladder logic programB) may be used only in subroutines in programs for Siemens PLCsC) are Short and Repeated coils, used in timing programsD) may be used instead of a seal-in arrangement to provide latching
What are the disadvantages of ratioed NMOS logic circuits?
6. Which of the following is not a type of signal is... a. analog signalb. Chain signalc. Binary signald. Dict signale. digital signal
answer the ff. tnxxxxxxx
18.) Choose the 8088 signals that are used to generate ROMRD. a.) IORD b.) IO/M c.) ALE d.) WR e.) RD
None
Q4: Suggest a control gate drive circuit for a Triac, which is used to control a fan regulator. The gate signals should be synchronized with the input voltage. Draw the complete: 1. Circuit diagram with the load and 2. The waveform of the input and output voltages. ) Q.13 Indicate whether the following statements are correct or not then correct the incorrect statements 1) the multi pulse selected notching technique used in inverter is used to eliminate the low order harmonics and to reduce switching frequency, 2) In 3-phase half-controlled half-wave rectifier, the firing angle can be varied from 0 to 180 degrees while in 6-phase half-controlled half-wave rectifier can be varied from 0 to 150 degrees Q.14 Indicate whether the following statements are correct or not then correct the incorrect statements 1) In rectifier circuits, lower pulse number and connecting either primary or secondary of 3- phase winding in delta will reduce the harmonics content of the drawr. current 2) In…
26. Draw the logic diagram for a modulus-18 Johnson counter. Show the timing diagram and write the sequence in tabular form.
4. How to use the PLL circuit and the logic circuit to comprise a doubler frequency circuit?
Draw a clock signal CLK with five 0-to-1 timing events, a nonzero setup time, tsu, and a nonzero hold time,th. Also draw one excitation input signal EI that follows the sequence 10110 and meets the setup and hold timerequirements. In the excitation input, the first bit in the sequence (1) occurs in time for the first clock timingevent, the second bit in the sequence (0) occurs in time for the second clock timing event, and so forth.