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Design a 2-digit decade counter that counts from 00 to 59 and repeats. Use two cascaded synchronous binary counters (74LS163) and other basic logic gates to implement. Simulate the complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform. . (Define the simulation timings for at least one full counting cycle from 0 to 59 and back to 0.)

Design a 2-digit decade counter that counts from 00 to 59 and repeats. Use two cascaded synchronous binary counters (74LS163) and other basic logic gates to implement. Simulate the complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform. . (Define the simulation timings for at least one full counting cycle from 0 to 59 and back to 0.)

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
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02 Design a 2-digit decade counter that counts from 00 to 59 and repeats. Use two cascaded synchronous binary counters (74LS163) and other basic logic gates to implement. Simulate the complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform.. (Define the simulation timings for at least one full counting cycle from 0 to 59 and back to 0.) Q3 Repeat Q2, modify the design to implement a 2-digit decade counter that counts from 33 to 77 and repeats. Use two cascaded synchronous binary counters (74LS163) and other basic logic gates to implement. Simulate the complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform. (Define the simulation timings for at least one full counting cycle from 33 to 77 and back to 33.)
Transcribed Image Text:02 Design a 2-digit decade counter that counts from 00 to 59 and repeats. Use two cascaded synchronous binary counters (74LS163) and other basic logic gates to implement. Simulate the complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform.. (Define the simulation timings for at least one full counting cycle from 0 to 59 and back to 0.) Q3 Repeat Q2, modify the design to implement a 2-digit decade counter that counts from 33 to 77 and repeats. Use two cascaded synchronous binary counters (74LS163) and other basic logic gates to implement. Simulate the complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform. (Define the simulation timings for at least one full counting cycle from 33 to 77 and back to 33.)
a) Design a single-digit decade counter that counts from 0 to 9 and repeats. The single-digit decade counter should be built by a cascaded synchronous binary counter (74LS163) and other basic logic gates. Simulate the complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform. (Define the simulation timings for at least one full counting cycle from 0 to 9 and back to 0.) (Hint: Use the DigClock input from the SOURCE as shown below and setup the CLK ONTIME and OFFTIME accordingly for the clock source.) 1/6 Pat DigClock Part List OFFTIME = SuS DSTM1 ONTIME = DELAY= STARTVAL = 0 OPPVAL = 1 Sus EUK FleStim AC Lbrajes Design Cache b) Read the specification of 74LS47 (BCD-to-7-Segment Decoder shown in Appendix) to see how the logic IC operates to drive a 7-segment LED display. Draw the circuit connection of the decade counter in (a) and the decoder to display the count value on the 7-segment LED display. Further explain why common anode configuration is needed for our 7-segment display rather than the common cathode configuration.
Transcribed Image Text:a) Design a single-digit decade counter that counts from 0 to 9 and repeats. The single-digit decade counter should be built by a cascaded synchronous binary counter (74LS163) and other basic logic gates. Simulate the complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform. (Define the simulation timings for at least one full counting cycle from 0 to 9 and back to 0.) (Hint: Use the DigClock input from the SOURCE as shown below and setup the CLK ONTIME and OFFTIME accordingly for the clock source.) 1/6 Pat DigClock Part List OFFTIME = SuS DSTM1 ONTIME = DELAY= STARTVAL = 0 OPPVAL = 1 Sus EUK FleStim AC Lbrajes Design Cache b) Read the specification of 74LS47 (BCD-to-7-Segment Decoder shown in Appendix) to see how the logic IC operates to drive a 7-segment LED display. Draw the circuit connection of the decade counter in (a) and the decoder to display the count value on the 7-segment LED display. Further explain why common anode configuration is needed for our 7-segment display rather than the common cathode configuration.
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