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Clemson University *

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425

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Electrical Engineering

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Oct 30, 2023

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Name :- Anirudh Kumar ASUID:- akuma282 EEE 425/591 LAB #02 1. Transistor Sizes Gate Name NMOS Width (nm) PMOS Width (nm) INVx03 945 1134 NOR 2x05 2127 5104 2. Create and Test Schematic a. (1) INVx03 schematic (2) NOR schematic
Name :- Anirudh Kumar ASUID:- akuma282 (3) *insert caption here
Name :- Anirudh Kumar ASUID:- akuma282 Figure 4 represents the INV and NOR Test Harnesses
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Name :- Anirudh Kumar ASUID:- akuma282 Figure 5 represents the Inverter Delay of 50% the Low to High (Left) and the High to Low (Right) Measurement Plots Cell 1 Delay Measurement Plot Spec Measured Value %50 Delay of High to Low 14.2 ps %50 Delay of Low to High 13.7 ps
Name :- Anirudh Kumar ASUID:- akuma282 (2) Spec Measured Value %50 Delay of High to Low 21.5 ps %50 Delay of Low to High 18.4 ps Cell 2 Delay Measurement Plot Figure 6 represents the NAND Delay of 50% the High to Low (Left) and the Low to High (Right) Measurement Plots 3. Layout Design a. (1) *insert caption here
Name :- Anirudh Kumar ASUID:- akuma282 (2) Figure 7 represents the layout view of the Inverter
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Name :- Anirudh Kumar ASUID:- akuma282 Figure 8 represents the NOR Layout b. (1) Cell 1 Layout and DRC Pass Cell 1
Name :- Anirudh Kumar ASUID:- akuma282 Figure 10 represents the Inverter Layout and LVS Pass Figure 11 represents the NOR Layout and DRC Pass Figure 12 represents the NOR Layout and LVS Pass

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