Lab1_Template

Apart from the variations in the process parameters, different portions of the design may also see different power supply voltage and temperature. All these differences can arise due to, (i) IR drop variation (ii) Voltage threshold variation of PMOS or NMOS device (iii) Channel length variation (iv) Interconnect metal etch or thickness variations A. i and ii B. i and iii C. ii and iv D. All of above

5. MOSFET's can be either NMOS or PMOS and can also: a. Glow in the dark b. Come as Enhancement mode or Depletion Mode c. Make a noise when current flows d. Not be used as switches

--- -- ----- Q9. Determine the mode of operation of a NMOS transistor when its terminal voltages are VGS = 3V, VDs = 1V, and VT = 1V? —-— OFF com_ Saturation Linear G D S

Given Id = 14mA and Vgs = 1V, determine Vp id Idss = 9.5mA for a depletion-type MOSFET. a. 5.34V b. 4.67V c. 7.87V %3D %3D d. 3.6V

1. Explain the I-V characteristics of the BJTS (IC-VCE) and MOSFETS (ID-VDs) by explaining the working mode of the devices on the I-V curves.

2.    Text Problems 4.4 and 4.8 for NMOS and Text Problem 4.47 for PMOS Some additional basic calculations to provide experience in units and nomenclature. Organize your results in a table. Page 160 (NMOS) and 161 (PMOS) has a table defining the relationships for key FET model parameters.

Write true or false for each statement 1) Phosphorous ions are implanted into active areas of NMOS transistors. 2) P-well is required for PMOS transistors if lightly doped p-type silicon wafer is used as a substrate. 3) Silicon dioxide is a very good conductor like metal 1 layer. 4) Aluminum is used for making a gate terminal on top of a SiO2 layer in CMOS fabrication. 5) Photolithography is a process of implanting atoms into the silicon substrate to make transistors.

1. Moore's Law: 1) What is Moore's Law about? 2) Why we have been used Moore's law to predict computer performance before multicore? 3) What limits the performance scaling based on Moore's law

Consider a digital logic circuit with two diodes as shownin figure 1. The diodes D1 and D2 are ideal (i.e. Vy = 0). 12 D ov, out 10 D2 5V 50kO Figure 1 A digital logic circuit with two ideal diodes A. Complete the equivalent circuit below and determine the output voltage vout oV and v, = 5V. Verify the conduction states of diodes by finding the current through D, and the voltage across D, when vị = Note that the output voltage is the same when v, = 5V and v, = 0V. 12 D out 12 D2 5V 50k2 Complete the equivalent circuit below and determine the output voltage vout when vị = v2 = В. 5V. 1Ω D Qut 10 5V 50k2 B.

Q2. a) Define and describe the Q-point, DC load-line, and AC load-line. b) Is a JFET a voltage controlled or current controlled device? c) What are the roles of the resistor Rs and Rp in a JFET bias circuit?

Text Problems 4.4 and 4.8 for NMOS and Text Problem 4.47 for PMOS Some additional basic calculations to provide experience in units and nomenclature. Organize your results in a table. Page 160 (NMOS) and 161 (PMOS) has a table defining the relationships for key FET model parameters.

The ______ terminal of the JFET is the equivalent of the Collector terminal of a BJT. a.Drain b.Source c.None of these d.Gate

IV. In the circuit with a silicon transistor, as shown in the +Vcc Figure, if Viegic = 3.6 V, Vcc = 10 V, VLED = 2.3 V, RE = 270 2, B = 200, 1. identify the type of transistor in use and label the three terminals in the figure. logic input 2. find the base current. 3. find the collector current. 4. find the collector-emitter voltage. RE

Which of the following(s) is(are) NOT a feature of short channel transistors? (Could be multiple answers) a) thin gate oxide b) heavy substrate doping c) low source/drain resistance d) shallow source/drain junction