BJT Exploration 1_NPN DC Biasing and CE Amp Configurations (1)

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Feb 20, 2024

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BJT Exploration 1 NPN DC Biasing and Common-Emitter Amplifier Configurations: Part I: NPN DC Biasing Figure 1: NPN DC Bias Circuit 1. DC Bias Circuit Design: A. Design the NPN DC Bias Circuit of Figure 1 using a β → ∞ model for the transistor (i.e. assuming the base current is zero): Determine the values of R C and R E so that the transistor operates at I C = 1.1 mA and V C = + 0.7 V . Outline each step of your design process and summarize your results in Table 1. (Reference: See Example 6.9 in the Sedra and Smith textbook, 8 th ed.). Include in Table 1 the standard 5% tolerance resistor values that are closest to your design values. Table 1: NPN DC Bias Circuit Design R C R E Resistor value from design Closest Standard 5% tol. Resistor value

B. Design Validation with Multisim Live Simulation: In Multisim Live create the design of the circuit of Figure 1 using the closest standard 5% tolerance resistor values for of R C and R E and the generic Multisim NPN model component. Insert voltage probes at nodes C and E and perform a DC Op (DC Operating Point) simulation to determine the simulated values of V C and V E . Calculate the value of I C and complete Table 2 to compare the DC Bias Point specifications in 1. A to what was achieved in the simulated circuit. Table 2 Validation of DC Bias Circuit Design V C V E I C Design Specification 0.7 V 1.1 mA Design Validation from Simulation Part II: Common-Emitter Amplifier Configurations Figure 2: NPN Common-Emitter Amplifier with Emitter Resistor Degeneration Configurations 2. Theory: A. Common-Emitter Amplifier with Emitter Resistor R E Degeneration:

The NPN BJT amplifier of Figure 2 is configured as a Common-Emitter with Emitter Resistor Degeneration amplifier. With S2 Open, the total emitter resistance, R E = R E1 + R E2 , in the emitter branch provides a high level of DC bias stability to this design, however, when left un-bypassed it results in significant degeneration of the magnitude of the small-signal voltage gain, A v . The theoretical small-signal voltage gain of the Common-Emitter with Emitter Resistor Degeneration configuration under No Load (S1 Open) is given by: A v = v 0 v i = − ∝ R C ∝ g m + R E Where ∝ = β 1 + β β→∞ → 1 and the value of the small-signal transconductance depends on the DC bias point and is given as: g m = I C 25 mV B. Common-Emitter Amplifier with partial Emitter Resistor R E1 Degeneration: (S2 Closed) With S2 Closed, the R E2 part of R E is bypassed through capacitor C 3 removing it’s degeneration effect on the small-signal voltage gain. Since capacitors are open-circuits to DC, even with S2 Closed, the total emitter resistor R E still provides the desired DC bias stability to this design. Once R E2 is bypassed, the achievable value of the small-signal voltage gain, A v becomes much larger. The theoretical small-signal voltage gain of the Common-Emitter Configuration with R E1 ( R E2 bypassed) (S2 Closed) under No Load (S1 Open) becomes: A v = v 0 v i = − ∝ R C ∝ g m + R E 1 Using the results of the Multisim Live simulated DC bias point of 1. B. and V tn = 2.2 V , calculate the theoretical values of g m and the voltage gains of (i) the Common-Source with Source Resistor Degeneration configuration under No Load (S1 Open) and (ii) the Common- Source configuration under No Load (S1 Open). Summarize your results in Table 3. Table 3 Small-signal Properties of NPN CE Amplifier Configurations Transistor transconductance, g m (mA/V) No load voltage gain of CE with R E Emitter Degeneration, (S2 Open) A v (V/V) No load voltage gain of CE with R E1 Emitter Degeneration, (S2 Closed) A v (V/V)

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3. Simulation: In Multisim Live create the design of the NPN Common-Emitter Amplifier Configuration of Figure 2 in the schematic capture window. Make your layout similar to Figure 2 using the generic Multisim NPN model component. First, perform a DC Op simulation to verify that the DC operating point ( V C and V E ) values are as expected. Next, perform two Transient simulations to determine the voltage gain of each configuration: (i) S2 Open; the Common-Emitter with R E Emitter Resistor Degeneration configuration under No Load (S1 Open) and (ii) S2 Closed; the Common-Emitter with R E1 Emitter Resistor Degeneration configuration under No Load (S1 Open). In each case, adjust the End time of the Transient simulation to 5e-3 s (5ms) to capture about five cycles of the 1 kHz test signal. Determine the No Load voltage gain for each configuration and export the Grapher image of the input and output voltage waveforms. Include these results in your report to compare to theory and experimentation. 4. Physical Experiment: On your breadboard, build the Common-Emitter Amplifier Configurations of Figure 2. [Use the 2N3904 NPN transistor from your parts kit]. Pay close attention to properly identifying and connecting the 2N3904 Collector, Base, and Emitter leads. Refer to the 2N3904 transistor datasheet. Also, pay close attention to the polarity connections on the electrolytic capacitors, C 1 , C 2 , and C 3 . For the physical experiment, you can replace switches S1 and S2 with simple jumper- wires. As always, use best practices when building and working with the breadboard prototype circuit. Perform the physical experiment using the AD2 and Waveforms Instrumentation in the same fashion as you did the Multisim Live simulations. Record data and export oscilloscope display images to include in your report for comparison. Additionally, for the Common-Emitter with R E1 Degeneration configuration (S2 Closed), record data and export the oscilloscope display image with S1 Closed ... i.e. measure the voltage gain with a load R L = 390 Ω connected. Compare the No Load voltage gain to the loaded voltage gain. Explain your results in the context of the output resistance of the CE configuration small-signal equivalent circuit model. 5. Submit a report of your exploration. (One report per lab group). Compare and discuss your results (e.g. Are the results what you expected? How does theory, simulation, and experiment compare, etc.?), draw conclusions from your exploration (one or two paragraphs).