Explanation of Solution
Cache Addressing:
The primary storage hierarchy contains cache lines that are grouped into sets. If each set contains k lines then we say that the cache is k-way associative.
A data request has an address specifying the location of the requested data. Each cache-line sized chunk of data from the lower level can only be placed into one set. The set that it can be placed into depends on its address.
The number of cache sets is equal to the number of cache blocks divided by the number of ways of associativity.
The least significant bits are used to determine the block offset.
For example:
One needs to consider the following set associative (S, E, B, m) = (8, 4, 4, 13). The derived value will be as follows:
The Index (CI):
The block off set (CO):
The tag bit (CT):
Hence, the “2” lower bits are block offsets (CO); followed by 3 sets of bit index (CI) and the remaining bits are tag bits (CT).
The following table gives the parameters for a number of different caches and the number of cache sets(S), tag bits(t), set index bits (s) and block offset bits (b) are defined.
Cache | m | C | B | E | S | t | s | b |
1 | 32 | 1024 | 4 | 1 | 256 | 22 | 8 | 2 |
2 | 32 | 1024 | 8 | 4 | 32 | 24 | 5 | 3 |
3 | 32 | 1024 | 32 | 32 | 1 | 27 | 0 | 5 |
The values for the above table are described below:
For cache-1:
It is given that
Hence:
For cache-2:
It is given that
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Chapter 6 Solutions
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