COMPUTER SYSTEMS&MOD MSGT/ET SA AC PKG
COMPUTER SYSTEMS&MOD MSGT/ET SA AC PKG
3rd Edition
ISBN: 9780134671123
Author: Bryant
Publisher: PEARSON
Question
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Chapter 6, Problem 6.38HW

A)

Program Plan Intro

Given Information:

The given code is:

// define structure

square point_color

{

// variable declaration

int c;

int m;

int y;

int k;

};

// declare structure array

struct point_color square[16][16];

int i,j;

// traverse through the array

for(i=0;i<16;i++)

{

//traverse through elements

for(j=0;j<16;j++)

{

//square all elements of the 2-D array

square[i][j].c=0;

square[i][j].m=0;

square[i][j].y=1;

square[i][j].k=0;

}

}

Write hit:

If the information in the cache is reserved or in dirty state then the cache line is updated in its place without updating memory set from its state to dirty.

  • If the state of information is in valid state then it executes a write-through operation.
  • It then updates the memory and block and changes its blocked state to reserved state.

Write miss:

A partial cache line write is handed as a read miss followed by a write hit. All the other caches are left in the invalid state and the reserved state is occupied by the current state.

B)

Program Plan Intro

Given Information:

The given code is:

// define structure

square point_color

{

// variable declaration

int c;

int m;

int y;

int k;

};

// declare structure array

struct point_color square[16][16];

int i,j;

// traverse through the array

for(i=0;i<16;i++)

{

//traverse through elements

for(j=0;j<16;j++)

{

//square all elements of the 2-D array

square[i][j].c=0;

square[i][j].m=0;

square[i][j].y=1;

square[i][j].k=0;

}

}

Write hit:

If the information in the cache is reserved or in dirty state then the cache line is updated in its place without updating memory set from its state to dirty.

  • If the state of information is in valid state then it executes a write-through operation.
  • It then updates the memory and block and changes its blocked state to reserved state.

Write miss:

A partial cache line write is handed as a read miss followed by a write hit. All the other caches are left in the invalid state and the reserved state is occupied by the current state.

C)

Program Plan Intro

Given Information:

The given code is:

//define structure

square point_color

{

// variable declaration

int c;

int m;

int y;

int k;

};

// declare structure array

struct point_color square[16][16];

int i,j;

// traverse through the array

for(i=0;i<16;i++)

{

//traverse through elements

for(j=0;j<16;j++)

{

//square all elements of the 2-D array

square[i][j].c=0;

square[i][j].m=0;

square[i][j].y=1;

square[i][j].k=0;

}

}

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