Microelectronics: Circuit Analysis and Design
4th Edition
ISBN: 9780073380643
Author: Donald A. Neamen
Publisher: McGraw-Hill Companies, The
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Question
Chapter 17, Problem 17.6TYU
(a)
To determine
The maximum value of the fan out for the low output condition.
(b)
To determine
The value of the maximum fan out.
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Students have asked these similar questions
Q2. Figure Q2 shows a block diagram with an input of C(s) and an output R(s).
a)
C(s)
K₁
R(s)
K2
1 + 5s
1+2s
Figure Q2. Block diagram of control system.
Simply the block diagram to get the transfer function of the system C(s)/R(s).
b)
What is the order of the system?
c)
What is the gain of the system?
d) Determine the values of K₁ and K₂ to obtain a natural frequency w of
0.5 rad/s and damping ratio of 0.4.
e) What is the rise time and overshoot of the system with a unit step input?
Q4.
a) A purely derivative controller (i.e. with a zero at the origin only) is defined
by an improper transfer function. Considering its asymptotic behaviour,
explain why a purely derivative controller is difficult to implement in
practice. Relate your explanation to the potential limitations on system
performance.
b) Discuss the potential issues faced by a control system with a large cut-off
frequency. Relate your discussion to the implications on system
performance.
c)
The transfer function of a lag compensator is given by
2
KPID(S) = 2.2++0.2s
S
By using the asymptotic approximation technique:
(i) Obtain the standard form and corner frequency for each individual
component of KPID(S).
(ii) Clearly describe the asymptotic behaviour of each individual
component of KPID(S).
Module Code: EN2058
Q1. a) List the advantages and disadvantages of a closed loop system compared to
an open loop system.
b)
c)
What is the procedure for designing a control system for a bread toaster?
An RC circuit is given in Figure Q1. vi(t) and v(t) are the input and output
voltages.
(i) Derive the transfer function of the circuit.
(ii) With a unit step change vi(t) applied to the circuit, derive and sketch the
time response of the circuit.
R1 R2
v₁(t)
R3 C1
vo(t)
R₁ =R2 = 10 k
R3 = 100 kn C₁ = 100 μF
Figure Q1. RC circuit.
(iii) Assuming zero initial conditions, obtain the impulse and ramp responses
of the circuit from the step response derived in (ii). Sketching is not
needed.
Chapter 17 Solutions
Microelectronics: Circuit Analysis and Design
Ch. 17 - Consider the differential amplifier circuit in...Ch. 17 - Prob. 17.2EPCh. 17 - The reference circuit in Figure 17.5 is to be...Ch. 17 - Assume the maximum currents in Q3 and Q4 of the...Ch. 17 - Prob. 17.5EPCh. 17 - Prob. 17.6EPCh. 17 - Prob. 17.1TYUCh. 17 - Prob. 17.2TYUCh. 17 - Prob. 17.7EPCh. 17 - Prob. 17.3TYU
Ch. 17 - The ECL circuit in Figure 17.19 is an example of...Ch. 17 - Consider the basic DTL circuit in Figure 17.20...Ch. 17 - The parameters of the TIL NAND circuit in Figure...Ch. 17 - Prob. 17.10EPCh. 17 - Prob. 17.5TYUCh. 17 - Prob. 17.6TYUCh. 17 - Prob. 17.7TYUCh. 17 - Prob. 17.8TYUCh. 17 - Prob. 17.11EPCh. 17 - Prob. 17.12EPCh. 17 - Prob. 17.9TYUCh. 17 - Prob. 17.10TYUCh. 17 - Prob. 17.11TYUCh. 17 - Prob. 1RQCh. 17 - Why must emitterfollower output stages be added to...Ch. 17 - Sketch a modified ECL circuit in which a Schottky...Ch. 17 - Explain the concept of series gating for ECL...Ch. 17 - Sketch a diodetransistor NAND circuit and explain...Ch. 17 - Explain the operation and purpose of the input...Ch. 17 - Sketch a basic TTL NAND circuit and explain its...Ch. 17 - Prob. 8RQCh. 17 - Prob. 9RQCh. 17 - Prob. 10RQCh. 17 - Explain the operation of a Schottky clamped...Ch. 17 - Prob. 12RQCh. 17 - Prob. 13RQCh. 17 - Sketch a basic BiCMOS inverter and explain its...Ch. 17 - For the differential amplifier circuit ¡n Figure...Ch. 17 - Prob. 17.2PCh. 17 - Prob. 17.3PCh. 17 - Prob. 17.4PCh. 17 - Prob. 17.5PCh. 17 - Prob. 17.6PCh. 17 - Prob. 17.7PCh. 17 - Prob. 17.8PCh. 17 - Prob. 17.9PCh. 17 - Prob. 17.10PCh. 17 - Prob. 17.11PCh. 17 - Prob. 17.12PCh. 17 - Prob. 17.13PCh. 17 - Prob. 17.14PCh. 17 - Prob. 17.15PCh. 17 - Prob. 17.16PCh. 17 - Prob. 17.17PCh. 17 - Prob. 17.18PCh. 17 - Consider the DTL circuit shown in Figure P17.19....Ch. 17 - Prob. 17.20PCh. 17 - Prob. 17.21PCh. 17 - Prob. 17.22PCh. 17 - Prob. 17.23PCh. 17 - Prob. 17.24PCh. 17 - Prob. 17.25PCh. 17 - Prob. 17.26PCh. 17 - Prob. 17.27PCh. 17 - Prob. 17.28PCh. 17 - Prob. 17.29PCh. 17 - Prob. 17.30PCh. 17 - Prob. 17.31PCh. 17 - Prob. 17.32PCh. 17 - Prob. 17.33PCh. 17 - For the transistors in the TTL circuit in Figure...Ch. 17 - Prob. 17.35PCh. 17 - Prob. 17.36PCh. 17 - Prob. 17.37PCh. 17 - Prob. 17.38PCh. 17 - Prob. 17.39PCh. 17 - Prob. 17.40PCh. 17 - Prob. 17.41PCh. 17 - Prob. 17.42PCh. 17 - Prob. 17.43PCh. 17 - Prob. 17.44PCh. 17 - Design a clocked D flipflop, using a modified ECL...Ch. 17 - Design a lowpower Schottky TTL exclusiveOR logic...Ch. 17 - Design a TTL RS flipflop.
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