Microelectronics: Circuit Analysis and Design
Microelectronics: Circuit Analysis and Design
4th Edition
ISBN: 9780073380643
Author: Donald A. Neamen
Publisher: McGraw-Hill Companies, The
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Chapter 17, Problem 17.33P

(a)

To determine

The value of the output voltage for different values of the load current.

(b)

To determine

The value of the load current when the output is shorted to ground.

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3. Describe the function of PLL circuit. 4. Describe the function of bandpass filter. ASK Modulator/Demodulator U1 VD Signal in VT out X1 W R1 VC Carrier in w x2 100K 3 Y1 4 Y2 AD633 Z VR1 10K VR1 Multiplier(1) I U2 Vx out X1 W R3 2 w x2 In2 100K 3 ۲۱ I Y2 AD633 Z VR2 R2 10K C4 100K VR2 Multiplier(2) +5V 200p R5 R6 R101K ww w 2.7K 22K 1N4148 D1 559 VE out D+ In(ac) 6 0H 200p HH 6 VLP out Vo out U3 VR 0.01 0.1u R8 VR3 ww 50K Envelope Detector 10K U3 LF356 VR3 LPF U4Σ LM311 Comparator U5 PLL in CS HH 14 SIGN IN 0.1u 6 CIA PC1OUT 2 PULSES PHASE(2) COMPARATOR OUT 13. C10 HT 150p R16 ww R12 VSO C6 200p VCO OUT 4 IK in R14 C9 18K 10 O w 7 Cle H VLO out 6 15K VCO 150p 06 11 R1 CD4046 VCO IN 9 VR5 1K 12 R2 0.0047u C7 I Demod C8 out 10 SOURCE FOLLOWER R11 100K INH COMP IN 5 3 VR4 +5V+12V GND-12V о HTO 0.1u R13 10K I PL VR5 Figure 18-10 KL-94005 module R15 U6Σ OP37 BPF
DUC 1. Is the waveform on VT out terminal an ASK modulated signal? TS PROD 2. Is the waveform on VT out terminal an OOK modulated signal? ASK Modulator/Demodulator U1 VD Signal in VT out X1 W R1 VC Carrier in w x2 100K 3 Y1 4 Y2 AD633 Z VR1 10K VR1 Multiplier(1) I U2 Vx out X1 W R3 2 w x2 In2 100K 3 ۲۱ I Y2 AD633 Z VR2 R2 10K C4 100K VR2 Multiplier(2) +5V 200p R5 R6 R101K ww w 2.7K 22K 1N4148 D1 559 VE out D+ In(ac) 6 0H 200p HH 6 VLP out Vo out U3 VR 0.01 0.1u R8 VR3 ww 50K Envelope Detector 10K U3 LF356 VR3 LPF U4Σ LM311 Comparator U5 PLL in CS HH 14 SIGN IN PC1OUT 2 0.1u 6 CIA PULSES PHASE(2) COMPARATOR OUT 13 C10 HT 150p R16 ww R12 VSO 18K C6 200p VCO OUT 4 IK in R14 C9 10 O w H VLO out 6 7 Cle 15K VCO 150p 06 11 R1 CD4046 VCO IN 9 VR5 1K 12 R2 0.0047u C7 I Demod C8 out 10 SOURCE FOLLOWER R11 100K INH COMP IN 5 3 VR4 +5V+12V GND-12V о HTO 0.1u R13 10K I PL Figure 18-10 KL-94005 module VR5 R15 U6Σ OP37 BPF
h e 6. Discuss the relationship between Vx out and VLP out signals. 7. Describe the function of comparator. ASK Modulator/Demodulator U1 VD Signal in VT out X1 W R1 VC Carrier in w x2 100K 3 Y1 4 Y2 AD633 Z VR1 10K VR1 Multiplier(1) I U2 Vx out X1 W R3 2 w x2 In2 100K 3 ۲۱ I Y2 AD633 Z VR2 R2 10K C4 100K VR2 Multiplier(2) +5V 200p R5 R6 R101K ww w 2.7K 22K 1N4148 D1 559 VE out D+ In(ac) 6 0H 200p HH 6 VLP out Vo out U3 VR 0.01 0.1u R8 VR3 ww 50K Envelope Detector 10K U3 LF356 VR3 LPF U4Σ LM311 Comparator U5 PLL in CS HH 14 SIGN IN 0.1u 6 CIA PC1OUT 2 PULSES PHASE(2) COMPARATOR OUT 13. C10 HT 150p R16 ww R12 VSO C6 200p VCO OUT 4 IK in R14 C9 18K 10 O w 7 Cle H VLO out 6 15K VCO 150p 06 11 R1 CD4046 VCO IN 9 VR5 1K 12 R2 0.0047u C7 I Demod C8 out 10 SOURCE FOLLOWER R11 100K INH COMP IN 5 3 VR4 +5V+12V GND-12V о HTO 0.1u R13 10K I PL VR5 Figure 18-10 KL-94005 module R15 U6Σ OP37 BPF

Chapter 17 Solutions

Microelectronics: Circuit Analysis and Design

Ch. 17 - The ECL circuit in Figure 17.19 is an example of...Ch. 17 - Consider the basic DTL circuit in Figure 17.20...Ch. 17 - The parameters of the TIL NAND circuit in Figure...Ch. 17 - Prob. 17.10EPCh. 17 - Prob. 17.5TYUCh. 17 - Prob. 17.6TYUCh. 17 - Prob. 17.7TYUCh. 17 - Prob. 17.8TYUCh. 17 - Prob. 17.11EPCh. 17 - Prob. 17.12EPCh. 17 - Prob. 17.9TYUCh. 17 - Prob. 17.10TYUCh. 17 - Prob. 17.11TYUCh. 17 - Prob. 1RQCh. 17 - Why must emitterfollower output stages be added to...Ch. 17 - Sketch a modified ECL circuit in which a Schottky...Ch. 17 - Explain the concept of series gating for ECL...Ch. 17 - Sketch a diodetransistor NAND circuit and explain...Ch. 17 - Explain the operation and purpose of the input...Ch. 17 - Sketch a basic TTL NAND circuit and explain its...Ch. 17 - Prob. 8RQCh. 17 - Prob. 9RQCh. 17 - Prob. 10RQCh. 17 - Explain the operation of a Schottky clamped...Ch. 17 - Prob. 12RQCh. 17 - Prob. 13RQCh. 17 - Sketch a basic BiCMOS inverter and explain its...Ch. 17 - For the differential amplifier circuit ¡n Figure...Ch. 17 - Prob. 17.2PCh. 17 - Prob. 17.3PCh. 17 - Prob. 17.4PCh. 17 - Prob. 17.5PCh. 17 - Prob. 17.6PCh. 17 - Prob. 17.7PCh. 17 - Prob. 17.8PCh. 17 - Prob. 17.9PCh. 17 - Prob. 17.10PCh. 17 - Prob. 17.11PCh. 17 - Prob. 17.12PCh. 17 - Prob. 17.13PCh. 17 - Prob. 17.14PCh. 17 - Prob. 17.15PCh. 17 - Prob. 17.16PCh. 17 - Prob. 17.17PCh. 17 - Prob. 17.18PCh. 17 - Consider the DTL circuit shown in Figure P17.19....Ch. 17 - Prob. 17.20PCh. 17 - Prob. 17.21PCh. 17 - Prob. 17.22PCh. 17 - Prob. 17.23PCh. 17 - Prob. 17.24PCh. 17 - Prob. 17.25PCh. 17 - Prob. 17.26PCh. 17 - Prob. 17.27PCh. 17 - Prob. 17.28PCh. 17 - Prob. 17.29PCh. 17 - Prob. 17.30PCh. 17 - Prob. 17.31PCh. 17 - Prob. 17.32PCh. 17 - Prob. 17.33PCh. 17 - For the transistors in the TTL circuit in Figure...Ch. 17 - Prob. 17.35PCh. 17 - Prob. 17.36PCh. 17 - Prob. 17.37PCh. 17 - Prob. 17.38PCh. 17 - Prob. 17.39PCh. 17 - Prob. 17.40PCh. 17 - Prob. 17.41PCh. 17 - Prob. 17.42PCh. 17 - Prob. 17.43PCh. 17 - Prob. 17.44PCh. 17 - Design a clocked D flipflop, using a modified ECL...Ch. 17 - Design a lowpower Schottky TTL exclusiveOR logic...Ch. 17 - Design a TTL RS flipflop.
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